Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	125359794	14522	0	0
claim_transition_if_regwen_rd_A	125359794	1632	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125359794	14522	0	0
T8	10024	0	0	0
T18	522550	17	0	0
T27	276404	7	0	0
T28	269688	5	0	0
T29	24391	0	0	0
T30	31970	0	0	0
T31	35774	0	0	0
T32	856	0	0	0
T45	0	6	0	0
T62	631004	0	0	0
T95	32469	0	0	0
T104	0	16	0	0
T105	0	14	0	0
T142	0	1	0	0
T143	0	8	0	0
T144	0	3	0	0
T145	0	6	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	125359794	1632	0	0
T8	10024	0	0	0
T28	269688	4	0	0
T29	24391	0	0	0
T30	31970	0	0	0
T31	35774	0	0	0
T32	856	0	0	0
T48	0	10	0	0
T62	631004	0	0	0
T83	4235	0	0	0
T95	32469	0	0	0
T96	3122	0	0	0
T111	0	25	0	0
T139	0	28	0	0
T146	0	5	0	0
T147	0	4	0	0
T148	0	7	0	0
T149	0	4	0	0
T150	0	256	0	0
T151	0	5	0	0