Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1709903	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1925304

1

T1

623

T2

1055

T3

12

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3303452	1			T1	524		T2	1091		T3	5
values[0x0]	164941	1			T1	245		T2	287		T3	8
values[0x1]	166814	1			T1	251		T2	289		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1358325	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2276882

1

T1

734

T2

1189

T3

14

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	9890	1			T1	8		T2	6		T4	6
valid_sources[0x01]	8774	1			T2	5		T3	1		T4	8
valid_sources[0x02]	8714	1			T1	15		T2	8		T4	6
valid_sources[0x03]	8958	1			T2	4		T4	2		T12	3
valid_sources[0x04]	8896	1			T1	3		T2	6		T10	1
valid_sources[0x05]	8499	1			T2	2		T4	5		T12	7
valid_sources[0x06]	8687	1			T2	12		T4	4		T12	27
valid_sources[0x07]	8755	1			T2	3		T4	4		T12	14
valid_sources[0x08]	8562	1			T2	5		T4	11		T12	2
valid_sources[0x09]	8582	1			T2	2		T4	11		T12	6
valid_sources[0x0a]	11152	1			T2	5		T4	10		T12	11
valid_sources[0x0b]	14066	1			T1	10		T2	11		T4	13
valid_sources[0x0c]	9773	1			T2	1		T4	8		T14	8
valid_sources[0x0d]	8886	1			T1	1		T2	5		T4	14
valid_sources[0x0e]	8638	1			T1	3		T2	3		T4	6
valid_sources[0x0f]	10393	1			T1	7		T2	5		T4	3
valid_sources[0x10]	8801	1			T1	13		T2	5		T4	6
valid_sources[0x11]	8738	1			T2	4		T4	10		T12	3
valid_sources[0x12]	62982	1			T2	13		T3	1		T4	4
valid_sources[0x13]	8691	1			T1	2		T2	8		T4	8
valid_sources[0x14]	9220	1			T2	9		T4	4		T12	14
valid_sources[0x15]	8558	1			T2	4		T4	5		T12	2
valid_sources[0x16]	8770	1			T1	1		T2	6		T4	8
valid_sources[0x17]	8699	1			T2	6		T4	11		T13	1
valid_sources[0x18]	8739	1			T1	9		T2	7		T4	7
valid_sources[0x19]	10488	1			T1	1		T2	11		T4	9
valid_sources[0x1a]	8651	1			T2	3		T4	6		T12	7
valid_sources[0x1b]	8696	1			T2	2		T4	9		T12	4
valid_sources[0x1c]	10610	1			T1	6		T2	1		T4	4
valid_sources[0x1d]	10001	1			T1	7		T2	2		T4	7
valid_sources[0x1e]	8967	1			T1	10		T2	7		T4	7
valid_sources[0x1f]	8773	1			T2	7		T3	1		T4	10
valid_sources[0x20]	8718	1			T1	3		T2	4		T4	7
valid_sources[0x21]	9907	1			T1	1		T2	7		T4	11
valid_sources[0x22]	9413	1			T1	10		T2	6		T4	8
valid_sources[0x23]	9186	1			T1	2		T2	10		T10	5
valid_sources[0x24]	8703	1			T2	8		T3	1		T10	6
valid_sources[0x25]	110310	1			T1	2		T2	16		T4	8
valid_sources[0x26]	9523	1			T1	25		T2	1		T4	4
valid_sources[0x27]	9077	1			T1	1		T2	7		T4	4
valid_sources[0x28]	9237	1			T1	22		T2	5		T4	15
valid_sources[0x29]	8840	1			T1	5		T2	12		T4	8
valid_sources[0x2a]	47246	1			T1	10		T2	12		T4	6
valid_sources[0x2b]	8477	1			T1	2		T2	4		T4	8
valid_sources[0x2c]	9773	1			T1	13		T2	5		T4	6
valid_sources[0x2d]	8991	1			T1	25		T4	3		T12	1
valid_sources[0x2e]	10308	1			T2	8		T4	8		T12	26
valid_sources[0x2f]	8910	1			T2	4		T3	1		T4	4
valid_sources[0x30]	98453	1			T1	14		T2	2		T4	10
valid_sources[0x31]	8623	1			T1	5		T2	7		T4	8
valid_sources[0x32]	10399	1			T2	8		T4	10		T12	5
valid_sources[0x33]	8571	1			T1	1		T2	4		T4	8
valid_sources[0x34]	8823	1			T1	4		T2	12		T4	10
valid_sources[0x35]	8642	1			T1	1		T2	9		T4	7
valid_sources[0x36]	9862	1			T1	50		T2	3		T10	7
valid_sources[0x37]	10157	1			T1	5		T2	6		T4	6
valid_sources[0x38]	8667	1			T2	7		T4	8		T12	7
valid_sources[0x39]	10664	1			T1	2		T2	8		T4	10
valid_sources[0x3a]	8786	1			T1	1		T2	5		T4	8
valid_sources[0x3b]	8791	1			T1	1		T2	4		T4	8
valid_sources[0x3c]	9053	1			T2	4		T4	12		T12	22
valid_sources[0x3d]	8826	1			T2	4		T4	9		T14	6
valid_sources[0x3e]	9472	1			T2	8		T4	6		T12	8
valid_sources[0x3f]	10360	1			T1	19		T2	4		T4	4
valid_sources[0x40]	8524	1			T2	9		T4	10		T12	33
valid_sources[0x41]	8705	1			T1	20		T2	6		T4	6
valid_sources[0x42]	10089	1			T1	5		T2	7		T4	5
valid_sources[0x43]	8691	1			T1	3		T2	7		T4	5
valid_sources[0x44]	27070	1			T1	3		T2	10		T4	6
valid_sources[0x45]	8772	1			T2	2		T4	4		T12	2
valid_sources[0x46]	9065	1			T2	7		T4	10		T12	5
valid_sources[0x47]	8696	1			T1	2		T2	8		T4	7
valid_sources[0x48]	18770	1			T2	8		T4	5		T12	16
valid_sources[0x49]	32024	1			T2	2		T4	8		T12	6
valid_sources[0x4a]	9699	1			T2	5		T10	1		T4	8
valid_sources[0x4b]	11149	1			T1	2		T2	6		T4	2
valid_sources[0x4c]	8652	1			T1	3		T2	4		T4	3
valid_sources[0x4d]	8608	1			T2	10		T4	13		T12	11
valid_sources[0x4e]	10466	1			T2	1		T4	6		T12	22
valid_sources[0x4f]	9676	1			T1	11		T2	3		T3	1
valid_sources[0x50]	9356	1			T2	6		T4	11		T12	9
valid_sources[0x51]	8999	1			T2	4		T4	4		T12	3
valid_sources[0x52]	8775	1			T1	9		T2	7		T4	10
valid_sources[0x53]	8870	1			T2	10		T4	6		T12	10
valid_sources[0x54]	12025	1			T2	8		T4	4		T12	19
valid_sources[0x55]	8973	1			T1	12		T2	9		T4	6
valid_sources[0x56]	25287	1			T1	10		T2	3		T4	8
valid_sources[0x57]	13016	1			T2	3		T4	9		T12	6
valid_sources[0x58]	58110	1			T1	6		T2	2		T4	13
valid_sources[0x59]	8507	1			T2	12		T4	4		T12	9
valid_sources[0x5a]	9521	1			T2	11		T4	7		T12	14
valid_sources[0x5b]	10097	1			T2	3		T4	9		T12	11
valid_sources[0x5c]	10429	1			T2	10		T4	11		T12	2
valid_sources[0x5d]	8740	1			T2	6		T4	9		T12	10
valid_sources[0x5e]	8995	1			T2	6		T4	6		T12	15
valid_sources[0x5f]	8940	1			T1	1		T2	13		T4	6
valid_sources[0x60]	12537	1			T1	18		T2	14		T4	11
valid_sources[0x61]	8991	1			T2	3		T3	1		T4	7
valid_sources[0x62]	8649	1			T2	2		T4	5		T12	22
valid_sources[0x63]	8603	1			T1	7		T2	11		T4	7
valid_sources[0x64]	11256	1			T2	12		T3	1		T4	3
valid_sources[0x65]	8819	1			T2	6		T4	7		T12	4
valid_sources[0x66]	8723	1			T1	6		T2	4		T3	1
valid_sources[0x67]	8470	1			T2	8		T4	8		T12	22
valid_sources[0x68]	8727	1			T1	4		T2	1		T4	8
valid_sources[0x69]	8807	1			T1	3		T2	2		T4	8
valid_sources[0x6a]	10142	1			T1	3		T2	9		T4	9
valid_sources[0x6b]	11152	1			T1	1		T2	5		T4	5
valid_sources[0x6c]	65966	1			T1	5		T2	9		T4	5
valid_sources[0x6d]	11257	1			T1	1		T2	7		T4	6
valid_sources[0x6e]	12961	1			T4	8		T12	16		T13	4
valid_sources[0x6f]	8630	1			T1	2		T2	9		T4	4
valid_sources[0x70]	8607	1			T1	11		T2	2		T4	4
valid_sources[0x71]	8890	1			T1	3		T2	5		T4	5
valid_sources[0x72]	8319	1			T1	19		T2	7		T4	9
valid_sources[0x73]	8749	1			T1	29		T2	11		T4	9
valid_sources[0x74]	8601	1			T2	5		T4	5		T12	20
valid_sources[0x75]	8603	1			T2	6		T4	6		T14	6
valid_sources[0x76]	10083	1			T1	2		T2	9		T3	1
valid_sources[0x77]	8865	1			T2	6		T4	9		T12	10
valid_sources[0x78]	8687	1			T2	7		T4	6		T12	2
valid_sources[0x79]	8692	1			T1	1		T2	2		T4	6
valid_sources[0x7a]	112412	1			T2	8		T4	7		T12	6
valid_sources[0x7b]	13407	1			T1	1		T2	9		T4	6
valid_sources[0x7c]	8430	1			T2	4		T4	8		T12	10
valid_sources[0x7d]	9977	1			T2	10		T4	4		T12	11
valid_sources[0x7e]	8909	1			T2	4		T10	1		T4	4
valid_sources[0x7f]	9959	1			T2	2		T4	14		T14	3
valid_sources[0x80]	9084	1			T1	1		T2	2		T10	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1639828

1

T1

200

T2

549

T4

472

values[0x0]

all_enables

biggest_size

142989

1

T1

214

T2

256

T3

7

values[0x1]

all_enables

biggest_size

142487

1

T1

209

T2

250

T3

5