Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	98055068	14064	0	0
claim_transition_if_regwen_rd_A	98055068	748	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98055068	14064	0	0
T39	1496	0	0	0
T64	0	12	0	0
T67	445352	0	0	0
T91	354089	2	0	0
T97	0	5	0	0
T116	0	6	0	0
T146	0	17	0	0
T147	0	4	0	0
T148	0	4	0	0
T149	0	8	0	0
T150	0	2	0	0
T151	0	1	0	0
T152	34133	0	0	0
T153	32006	0	0	0
T154	27116	0	0	0
T155	6723	0	0	0
T156	164328	0	0	0
T157	8418	0	0	0
T158	150476	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98055068	748	0	0
T59	12879	0	0	0
T100	34602	0	0	0
T101	1724	0	0	0
T102	5317	0	0	0
T103	2349	0	0	0
T104	6533	0	0	0
T105	35546	0	0	0
T138	0	41	0	0
T147	241771	15	0	0
T159	0	3	0	0
T160	0	7	0	0
T161	0	12	0	0
T162	0	3	0	0
T163	0	5	0	0
T164	0	6	0	0
T165	0	2	0	0
T166	0	10	0	0
T167	2411	0	0	0
T168	31521	0	0	0