Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1578051	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1788533

1

T1

284

T2

10

T3

675

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3035154	1			T1	253		T2	5		T3	508
values[0x0]	165061	1			T1	104		T2	7		T3	265
values[0x1]	166369	1			T1	113		T2	8		T3	231

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1253611	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2112973

1

T1

319

T2

10

T3

748

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8296	1			T3	5		T5	6		T12	2
valid_sources[0x01]	8316	1			T3	2		T5	2		T12	2
valid_sources[0x02]	8420	1			T3	3		T5	9		T12	5
valid_sources[0x03]	8477	1			T3	4		T5	6		T12	8
valid_sources[0x04]	8209	1			T3	7		T12	6		T6	1
valid_sources[0x05]	8342	1			T3	1		T5	1		T12	3
valid_sources[0x06]	10896	1			T3	9		T5	3		T12	9
valid_sources[0x07]	8204	1			T3	2		T12	6		T6	3
valid_sources[0x08]	8340	1			T3	8		T12	9		T13	20
valid_sources[0x09]	8267	1			T1	10		T3	3		T5	5
valid_sources[0x0a]	8391	1			T3	1		T5	3		T12	4
valid_sources[0x0b]	8448	1			T1	10		T3	4		T5	4
valid_sources[0x0c]	35747	1			T3	2		T5	10		T12	6
valid_sources[0x0d]	8912	1			T3	2		T12	8		T6	10
valid_sources[0x0e]	8902	1			T3	14		T5	7		T12	2
valid_sources[0x0f]	8660	1			T3	4		T5	1		T12	9
valid_sources[0x10]	8386	1			T3	6		T5	1		T12	7
valid_sources[0x11]	8268	1			T1	5		T3	1		T5	3
valid_sources[0x12]	8405	1			T3	1		T5	7		T12	7
valid_sources[0x13]	10123	1			T3	3		T5	2		T12	5
valid_sources[0x14]	12263	1			T3	1		T12	3		T13	3
valid_sources[0x15]	8321	1			T3	1		T12	5		T13	5
valid_sources[0x16]	8358	1			T1	6		T3	6		T5	3
valid_sources[0x17]	8729	1			T3	2		T5	7		T12	14
valid_sources[0x18]	8193	1			T3	9		T5	3		T12	8
valid_sources[0x19]	8674	1			T3	6		T12	8		T13	11
valid_sources[0x1a]	8435	1			T1	1		T3	1		T5	11
valid_sources[0x1b]	8496	1			T1	18		T5	2		T12	4
valid_sources[0x1c]	9741	1			T1	6		T3	3		T5	13
valid_sources[0x1d]	8522	1			T3	2		T5	8		T12	5
valid_sources[0x1e]	30226	1			T3	5		T5	6		T12	18
valid_sources[0x1f]	8344	1			T3	2		T5	4		T12	11
valid_sources[0x20]	8245	1			T3	4		T5	2		T12	8
valid_sources[0x21]	8182	1			T3	2		T5	6		T12	1
valid_sources[0x22]	9498	1			T3	5		T5	11		T12	4
valid_sources[0x23]	8926	1			T12	5		T6	4		T13	29
valid_sources[0x24]	8297	1			T5	4		T12	5		T15	2
valid_sources[0x25]	11208	1			T3	5		T5	9		T12	9
valid_sources[0x26]	8780	1			T3	9		T5	7		T12	4
valid_sources[0x27]	12381	1			T3	2		T12	5		T13	7
valid_sources[0x28]	8328	1			T3	5		T5	8		T12	8
valid_sources[0x29]	8502	1			T3	2		T5	4		T12	6
valid_sources[0x2a]	23238	1			T3	6		T5	4		T12	4
valid_sources[0x2b]	8323	1			T3	2		T5	1		T12	8
valid_sources[0x2c]	10488	1			T1	12		T3	8		T5	18
valid_sources[0x2d]	8557	1			T3	2		T5	13		T12	3
valid_sources[0x2e]	8177	1			T5	10		T12	3		T6	5
valid_sources[0x2f]	9710	1			T1	15		T3	1		T5	9
valid_sources[0x30]	9722	1			T5	2		T12	3		T13	3
valid_sources[0x31]	8558	1			T3	1		T5	10		T12	6
valid_sources[0x32]	8048	1			T1	2		T3	9		T12	11
valid_sources[0x33]	9402	1			T3	2		T5	4		T12	1
valid_sources[0x34]	8364	1			T3	3		T5	2		T12	7
valid_sources[0x35]	16609	1			T3	3		T5	3		T12	8
valid_sources[0x36]	7989	1			T3	3		T5	2		T12	2
valid_sources[0x37]	8878	1			T3	1		T12	5		T6	2
valid_sources[0x38]	10080	1			T3	6		T5	16		T12	5
valid_sources[0x39]	9043	1			T3	1		T5	4		T12	5
valid_sources[0x3a]	25236	1			T1	3		T3	2		T5	12
valid_sources[0x3b]	8671	1			T1	19		T3	7		T12	4
valid_sources[0x3c]	8477	1			T3	3		T12	7		T6	5
valid_sources[0x3d]	8757	1			T3	1		T12	5		T6	8
valid_sources[0x3e]	8446	1			T3	7		T5	18		T12	5
valid_sources[0x3f]	8131	1			T3	1		T5	1		T12	2
valid_sources[0x40]	11437	1			T1	1		T3	6		T12	2
valid_sources[0x41]	8120	1			T3	2		T5	1		T12	4
valid_sources[0x42]	83683	1			T3	4		T5	3		T12	5
valid_sources[0x43]	8217	1			T1	1		T3	5		T5	5
valid_sources[0x44]	8977	1			T3	10		T5	8		T12	5
valid_sources[0x45]	9731	1			T3	3		T5	8		T12	3
valid_sources[0x46]	8237	1			T3	4		T5	2		T12	7
valid_sources[0x47]	9999	1			T3	4		T5	12		T12	7
valid_sources[0x48]	10132	1			T1	1		T3	3		T5	12
valid_sources[0x49]	8599	1			T3	1		T5	2		T12	13
valid_sources[0x4a]	8466	1			T3	4		T5	2		T12	5
valid_sources[0x4b]	8220	1			T3	2		T12	4		T13	21
valid_sources[0x4c]	8304	1			T1	4		T3	6		T5	11
valid_sources[0x4d]	8014	1			T3	3		T5	2		T12	3
valid_sources[0x4e]	8381	1			T3	1		T12	7		T6	6
valid_sources[0x4f]	8500	1			T3	4		T5	2		T12	6
valid_sources[0x50]	8582	1			T3	5		T5	5		T12	10
valid_sources[0x51]	8234	1			T3	4		T5	8		T12	11
valid_sources[0x52]	8659	1			T3	3		T5	7		T12	5
valid_sources[0x53]	8299	1			T3	3		T5	11		T12	5
valid_sources[0x54]	8347	1			T3	3		T13	10		T15	4
valid_sources[0x55]	8085	1			T5	9		T12	3		T13	9
valid_sources[0x56]	62829	1			T3	5		T12	8		T6	2
valid_sources[0x57]	8490	1			T1	26		T3	3		T5	5
valid_sources[0x58]	8437	1			T1	12		T3	1		T5	4
valid_sources[0x59]	8356	1			T5	6		T12	9		T13	4
valid_sources[0x5a]	185143	1			T3	8		T5	7		T12	4
valid_sources[0x5b]	88375	1			T3	11		T5	1		T12	3
valid_sources[0x5c]	8201	1			T1	1		T3	5		T5	4
valid_sources[0x5d]	9343	1			T3	5		T5	4		T12	7
valid_sources[0x5e]	8305	1			T3	9		T5	15		T12	6
valid_sources[0x5f]	8604	1			T1	12		T3	4		T12	6
valid_sources[0x60]	80561	1			T1	1		T3	3		T5	2
valid_sources[0x61]	8251	1			T3	3		T5	8		T12	7
valid_sources[0x62]	8741	1			T3	4		T12	7		T13	17
valid_sources[0x63]	8427	1			T3	3		T12	5		T13	17
valid_sources[0x64]	12120	1			T3	2		T5	10		T12	9
valid_sources[0x65]	79976	1			T5	15		T12	5		T13	12
valid_sources[0x66]	49512	1			T3	6		T12	6		T13	7
valid_sources[0x67]	8258	1			T3	5		T5	4		T12	4
valid_sources[0x68]	10341	1			T1	13		T3	9		T5	1
valid_sources[0x69]	8221	1			T3	2		T5	1		T12	6
valid_sources[0x6a]	8345	1			T3	11		T12	7		T13	5
valid_sources[0x6b]	8337	1			T1	32		T3	7		T5	6
valid_sources[0x6c]	8296	1			T1	3		T3	4		T5	4
valid_sources[0x6d]	8573	1			T3	2		T5	7		T12	6
valid_sources[0x6e]	9325	1			T3	2		T5	9		T12	3
valid_sources[0x6f]	9499	1			T1	8		T5	5		T12	9
valid_sources[0x70]	8228	1			T3	8		T5	14		T12	2
valid_sources[0x71]	9396	1			T3	6		T5	3		T12	6
valid_sources[0x72]	12541	1			T1	1		T3	4		T5	14
valid_sources[0x73]	8464	1			T1	10		T3	4		T5	12
valid_sources[0x74]	9287	1			T3	3		T12	5		T13	9
valid_sources[0x75]	8341	1			T3	4		T12	8		T6	3
valid_sources[0x76]	23133	1			T3	4		T5	3		T12	2
valid_sources[0x77]	8411	1			T3	3		T5	16		T12	5
valid_sources[0x78]	8641	1			T1	2		T3	3		T12	4
valid_sources[0x79]	9109	1			T1	19		T3	8		T5	4
valid_sources[0x7a]	8621	1			T3	6		T12	7		T13	3
valid_sources[0x7b]	8521	1			T1	1		T3	8		T5	15
valid_sources[0x7c]	8397	1			T3	2		T5	5		T12	4
valid_sources[0x7d]	8514	1			T3	9		T5	3		T12	4
valid_sources[0x7e]	8363	1			T3	3		T5	10		T12	2
valid_sources[0x7f]	9639	1			T3	5		T5	3		T12	4
valid_sources[0x80]	8466	1			T3	1		T5	7		T12	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1502967

1

T1

123

T3

242

T4

733

values[0x0]

all_enables

biggest_size

142996

1

T1

76

T2

6

T3

228

values[0x1]

all_enables

biggest_size

142570

1

T1

85

T2

4

T3

205