Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.72	100.00	83.10	99.89		100.00	90.62	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	98198430	15593	0	0
claim_transition_if_regwen_rd_A	98198430	1431	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98198430	15593	0	0
T26	60663	0	0	0
T29	1405	0	0	0
T44	0	15	0	0
T91	130135	1	0	0
T93	0	15	0	0
T103	0	6	0	0
T104	0	1	0	0
T119	0	5	0	0
T153	0	5	0	0
T154	0	16	0	0
T155	0	7	0	0
T156	0	6	0	0
T157	37073	0	0	0
T158	19875	0	0	0
T159	299029	0	0	0
T160	39158	0	0	0
T161	13451	0	0	0
T162	33439	0	0	0
T163	18520	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	98198430	1431	0	0
T103	196176	6	0	0
T106	1494	0	0	0
T107	1313	0	0	0
T108	35766	0	0	0
T109	24284	0	0	0
T110	1357	0	0	0
T111	7886	0	0	0
T112	3376	0	0	0
T113	29851	0	0	0
T114	5334	0	0	0
T123	0	13	0	0
T129	0	4	0	0
T150	0	11	0	0
T164	0	5	0	0
T165	0	7	0	0
T166	0	7	0	0
T167	0	8	0	0
T168	0	29	0	0
T169	0	6	0	0