Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1423610	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1638511

1

T1

670

T2

1737

T3

586

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2727194	1			T1	641		T2	2171		T3	395
values[0x0]	166906	1			T1	196		T2	405		T3	221
values[0x1]	168021	1			T1	228		T2	395		T3	227

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1128985	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1933136

1

T1

759

T2

1996

T3

644

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	11205	1			T1	7		T2	9		T3	2
valid_sources[0x01]	12381	1			T2	4		T3	13		T12	2
valid_sources[0x02]	10031	1			T1	15		T2	7		T15	5
valid_sources[0x03]	11406	1			T1	7		T2	5		T3	1
valid_sources[0x04]	14853	1			T2	27		T3	1		T12	3
valid_sources[0x05]	11433	1			T1	5		T2	21		T12	3
valid_sources[0x06]	10856	1			T1	2		T2	8		T3	7
valid_sources[0x07]	47228	1			T2	6		T3	3		T12	5
valid_sources[0x08]	10995	1			T12	7		T15	2		T5	96
valid_sources[0x09]	10463	1			T1	1		T3	21		T12	2
valid_sources[0x0a]	12461	1			T2	4		T3	1		T12	8
valid_sources[0x0b]	10194	1			T1	7		T2	21		T12	1
valid_sources[0x0c]	10377	1			T1	15		T2	23		T12	5
valid_sources[0x0d]	18513	1			T1	15		T2	12		T3	1
valid_sources[0x0e]	12001	1			T1	2		T2	5		T12	2
valid_sources[0x0f]	13061	1			T1	1		T2	8		T3	14
valid_sources[0x10]	10838	1			T1	1		T2	8		T3	14
valid_sources[0x11]	10627	1			T1	3		T2	41		T12	6
valid_sources[0x12]	10249	1			T1	19		T2	16		T3	6
valid_sources[0x13]	10372	1			T1	4		T2	31		T3	12
valid_sources[0x14]	12001	1			T1	3		T2	7		T12	5
valid_sources[0x15]	10664	1			T2	3		T12	6		T15	2
valid_sources[0x16]	10836	1			T1	2		T2	10		T3	14
valid_sources[0x17]	10886	1			T1	2		T2	26		T3	1
valid_sources[0x18]	10749	1			T1	11		T2	22		T12	4
valid_sources[0x19]	10859	1			T1	8		T2	18		T12	5
valid_sources[0x1a]	10447	1			T1	6		T2	9		T12	3
valid_sources[0x1b]	13109	1			T1	5		T12	3		T13	1
valid_sources[0x1c]	10556	1			T1	1		T2	29		T3	16
valid_sources[0x1d]	29784	1			T1	14		T2	7		T12	4
valid_sources[0x1e]	21706	1			T12	2		T15	6		T5	114
valid_sources[0x1f]	12960	1			T1	3		T2	11		T12	6
valid_sources[0x20]	11917	1			T2	11		T3	1		T12	2
valid_sources[0x21]	10337	1			T1	10		T12	1		T15	7
valid_sources[0x22]	11464	1			T2	12		T3	11		T12	1
valid_sources[0x23]	11377	1			T1	1		T2	4		T12	3
valid_sources[0x24]	12994	1			T1	6		T2	1		T3	7
valid_sources[0x25]	10255	1			T2	6		T12	7		T13	1
valid_sources[0x26]	10432	1			T1	1		T2	17		T3	11
valid_sources[0x27]	9963	1			T1	2		T2	11		T12	8
valid_sources[0x28]	11495	1			T1	8		T2	13		T3	2
valid_sources[0x29]	10503	1			T1	3		T2	3		T12	2
valid_sources[0x2a]	11615	1			T1	3		T2	14		T3	20
valid_sources[0x2b]	10080	1			T1	3		T2	1		T12	8
valid_sources[0x2c]	11094	1			T2	5		T3	1		T12	4
valid_sources[0x2d]	10335	1			T1	3		T2	10		T3	5
valid_sources[0x2e]	10506	1			T1	6		T2	25		T12	5
valid_sources[0x2f]	10716	1			T1	20		T2	21		T12	6
valid_sources[0x30]	10559	1			T1	9		T3	6		T12	2
valid_sources[0x31]	10300	1			T1	1		T2	17		T12	7
valid_sources[0x32]	10552	1			T1	1		T2	8		T12	9
valid_sources[0x33]	12115	1			T1	5		T2	9		T12	6
valid_sources[0x34]	10255	1			T1	12		T2	7		T12	3
valid_sources[0x35]	9962	1			T1	1		T2	6		T3	11
valid_sources[0x36]	11559	1			T2	6		T12	5		T15	1
valid_sources[0x37]	10620	1			T1	2		T2	31		T3	2
valid_sources[0x38]	11144	1			T2	14		T3	1		T12	10
valid_sources[0x39]	10751	1			T1	4		T2	8		T12	3
valid_sources[0x3a]	10051	1			T1	7		T2	5		T12	4
valid_sources[0x3b]	54899	1			T1	7		T2	20		T3	7
valid_sources[0x3c]	12868	1			T1	4		T2	9		T12	4
valid_sources[0x3d]	11532	1			T1	7		T2	40		T12	7
valid_sources[0x3e]	20441	1			T2	28		T12	4		T15	2
valid_sources[0x3f]	10766	1			T2	33		T3	5		T12	11
valid_sources[0x40]	10454	1			T1	1		T2	6		T12	5
valid_sources[0x41]	11543	1			T2	8		T12	7		T15	5
valid_sources[0x42]	11836	1			T3	3		T12	5		T15	1
valid_sources[0x43]	10450	1			T1	3		T2	6		T3	5
valid_sources[0x44]	10775	1			T1	6		T2	4		T12	6
valid_sources[0x45]	13010	1			T1	4		T2	10		T12	4
valid_sources[0x46]	12663	1			T1	9		T2	29		T12	7
valid_sources[0x47]	30918	1			T1	5		T2	10		T12	4
valid_sources[0x48]	11892	1			T1	6		T3	3		T12	1
valid_sources[0x49]	10349	1			T12	3		T15	8		T5	139
valid_sources[0x4a]	10619	1			T1	2		T2	4		T3	2
valid_sources[0x4b]	10356	1			T2	1		T12	2		T15	3
valid_sources[0x4c]	10865	1			T2	4		T3	27		T12	4
valid_sources[0x4d]	9934	1			T1	2		T2	30		T3	1
valid_sources[0x4e]	10629	1			T1	6		T2	12		T12	7
valid_sources[0x4f]	16401	1			T1	2		T2	19		T3	4
valid_sources[0x50]	10432	1			T1	5		T12	1		T15	2
valid_sources[0x51]	10179	1			T1	1		T2	14		T3	7
valid_sources[0x52]	11251	1			T1	9		T2	29		T12	3
valid_sources[0x53]	10272	1			T2	19		T3	8		T12	4
valid_sources[0x54]	12283	1			T1	5		T2	3		T12	1
valid_sources[0x55]	10919	1			T1	1		T2	1		T12	6
valid_sources[0x56]	10638	1			T2	9		T12	1		T5	132
valid_sources[0x57]	11553	1			T2	5		T12	5		T5	130
valid_sources[0x58]	10926	1			T1	4		T2	2		T12	3
valid_sources[0x59]	10299	1			T2	7		T3	12		T12	6
valid_sources[0x5a]	11971	1			T3	5		T12	7		T15	3
valid_sources[0x5b]	15697	1			T1	7		T2	17		T12	8
valid_sources[0x5c]	12497	1			T2	2		T12	6		T5	108
valid_sources[0x5d]	10796	1			T1	3		T2	8		T3	11
valid_sources[0x5e]	10533	1			T1	5		T2	4		T3	1
valid_sources[0x5f]	11259	1			T1	11		T2	2		T12	1
valid_sources[0x60]	10404	1			T1	3		T2	10		T3	8
valid_sources[0x61]	10228	1			T1	4		T2	6		T12	1
valid_sources[0x62]	13243	1			T2	4		T12	1		T15	2
valid_sources[0x63]	10661	1			T1	2		T12	4		T15	2
valid_sources[0x64]	10122	1			T1	6		T2	7		T3	11
valid_sources[0x65]	10964	1			T1	5		T3	6		T12	4
valid_sources[0x66]	14578	1			T1	6		T2	33		T3	22
valid_sources[0x67]	10768	1			T1	2		T2	6		T12	4
valid_sources[0x68]	11866	1			T1	2		T2	8		T12	3
valid_sources[0x69]	11593	1			T1	5		T2	20		T3	27
valid_sources[0x6a]	10573	1			T1	3		T2	2		T12	1
valid_sources[0x6b]	11650	1			T1	18		T2	2		T12	7
valid_sources[0x6c]	10272	1			T1	3		T2	30		T3	4
valid_sources[0x6d]	10221	1			T1	4		T2	15		T12	4
valid_sources[0x6e]	10802	1			T2	19		T3	2		T12	9
valid_sources[0x6f]	20045	1			T1	3		T2	6		T3	11
valid_sources[0x70]	11824	1			T1	3		T2	9		T3	1
valid_sources[0x71]	12030	1			T12	3		T5	115		T17	3
valid_sources[0x72]	10141	1			T2	19		T12	5		T5	90
valid_sources[0x73]	10589	1			T1	2		T12	5		T5	131
valid_sources[0x74]	10634	1			T1	8		T2	10		T3	12
valid_sources[0x75]	18397	1			T1	1		T2	12		T12	6
valid_sources[0x76]	10751	1			T1	4		T2	11		T12	3
valid_sources[0x77]	10234	1			T2	12		T3	7		T12	3
valid_sources[0x78]	10291	1			T1	19		T2	9		T3	2
valid_sources[0x79]	10827	1			T1	11		T12	4		T13	1
valid_sources[0x7a]	11119	1			T1	3		T2	17		T3	18
valid_sources[0x7b]	10410	1			T2	10		T3	1		T12	4
valid_sources[0x7c]	10496	1			T2	4		T3	8		T12	1
valid_sources[0x7d]	13221	1			T1	6		T2	7		T12	7
valid_sources[0x7e]	10247	1			T1	8		T2	28		T12	6
valid_sources[0x7f]	10195	1			T1	1		T2	8		T12	3
valid_sources[0x80]	10295	1			T1	9		T2	6		T3	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1350594

1

T1

298

T2

1044

T3

202

values[0x0]

all_enables

biggest_size

144354

1

T1

174

T2

356

T3

194

values[0x1]

all_enables

biggest_size

143563

1

T1

198

T2

337

T3

190