Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	97460401	15737	0	0
claim_transition_if_regwen_rd_A	97460401	1579	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97460401	15737	0	0
T5	874941	1	0	0
T6	11604	0	0	0
T17	29083	0	0	0
T18	30065	0	0	0
T19	26968	0	0	0
T20	0	6	0	0
T26	5715	0	0	0
T27	1314	0	0	0
T45	36515	0	0	0
T50	29034	0	0	0
T58	0	12	0	0
T59	0	5	0	0
T71	37328	0	0	0
T106	0	2	0	0
T109	0	3	0	0
T143	0	11	0	0
T144	0	5	0	0
T145	0	8	0	0
T146	0	9	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	97460401	1579	0	0
T5	874941	6	0	0
T6	11604	0	0	0
T17	29083	0	0	0
T18	30065	0	0	0
T19	26968	0	0	0
T26	5715	0	0	0
T27	1314	0	0	0
T45	36515	0	0	0
T50	29034	0	0	0
T71	37328	0	0	0
T106	0	1	0	0
T112	0	7	0	0
T117	0	18	0	0
T119	0	9	0	0
T120	0	12	0	0
T144	0	15	0	0
T147	0	1	0	0
T148	0	7	0	0
T149	0	6	0	0