Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1863865	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

2085424

1

T1

496

T2

3401

T3

633

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	3602262	1			T1	421		T2	5784		T3	543
values[0x0]	173178	1			T1	196		T2	348		T3	252
values[0x1]	173849	1			T1	188		T2	340		T3	244

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1481768	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2467521

1

T1

568

T2

4041

T3

752

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13700	1			T2	14		T3	5		T16	1
valid_sources[0x01]	12849	1			T2	33		T3	1		T14	934
valid_sources[0x02]	11871	1			T2	7		T3	3		T13	1
valid_sources[0x03]	11864	1			T2	39		T3	4		T16	5
valid_sources[0x04]	13446	1			T2	32		T3	3		T41	7
valid_sources[0x05]	12512	1			T2	21		T3	4		T16	22
valid_sources[0x06]	13971	1			T2	4		T3	6		T41	6
valid_sources[0x07]	12996	1			T2	34		T3	2		T16	4
valid_sources[0x08]	12227	1			T2	29		T3	2		T16	1
valid_sources[0x09]	13780	1			T2	37		T16	11		T41	2
valid_sources[0x0a]	12291	1			T2	6		T12	37		T41	8
valid_sources[0x0b]	107354	1			T2	21		T3	4		T16	5
valid_sources[0x0c]	12152	1			T2	15		T3	16		T12	6
valid_sources[0x0d]	12227	1			T2	21		T16	27		T41	6
valid_sources[0x0e]	12374	1			T2	15		T3	5		T16	1
valid_sources[0x0f]	46356	1			T2	28		T3	2		T16	2
valid_sources[0x10]	16202	1			T2	14		T3	2		T22	1
valid_sources[0x11]	13685	1			T2	14		T3	2		T16	21
valid_sources[0x12]	13705	1			T2	22		T3	1		T16	25
valid_sources[0x13]	13362	1			T2	16		T3	9		T16	1
valid_sources[0x14]	14781	1			T2	16		T3	4		T16	1
valid_sources[0x15]	12635	1			T2	21		T3	3		T16	10
valid_sources[0x16]	29801	1			T2	22		T3	2		T16	9
valid_sources[0x17]	11860	1			T2	8		T3	3		T13	1
valid_sources[0x18]	12434	1			T2	34		T3	3		T16	6
valid_sources[0x19]	13878	1			T2	27		T3	8		T16	10
valid_sources[0x1a]	11986	1			T2	28		T22	1		T41	5
valid_sources[0x1b]	12769	1			T2	37		T16	2		T41	8
valid_sources[0x1c]	13167	1			T2	38		T3	9		T12	35
valid_sources[0x1d]	11929	1			T2	15		T3	4		T16	9
valid_sources[0x1e]	12476	1			T2	8		T3	1		T16	11
valid_sources[0x1f]	12120	1			T2	7		T3	2		T16	13
valid_sources[0x20]	12434	1			T2	32		T3	5		T16	1
valid_sources[0x21]	13262	1			T2	14		T16	1		T41	7
valid_sources[0x22]	12395	1			T2	15		T16	9		T41	2
valid_sources[0x23]	11915	1			T2	17		T3	3		T12	6
valid_sources[0x24]	13441	1			T2	56		T3	6		T16	18
valid_sources[0x25]	12379	1			T2	45		T3	7		T16	14
valid_sources[0x26]	81650	1			T2	9		T3	5		T16	21
valid_sources[0x27]	16236	1			T2	17		T3	1		T16	10
valid_sources[0x28]	13463	1			T2	10		T3	2		T16	9
valid_sources[0x29]	12444	1			T2	51		T3	8		T16	10
valid_sources[0x2a]	12819	1			T2	20		T3	6		T16	11
valid_sources[0x2b]	12025	1			T2	26		T3	2		T16	2
valid_sources[0x2c]	33525	1			T2	18		T3	2		T16	5
valid_sources[0x2d]	12357	1			T2	36		T3	6		T12	148
valid_sources[0x2e]	11990	1			T2	5		T12	17		T16	16
valid_sources[0x2f]	15119	1			T2	9		T3	3		T16	28
valid_sources[0x30]	12534	1			T2	26		T3	1		T13	1
valid_sources[0x31]	12384	1			T2	64		T3	1		T16	2
valid_sources[0x32]	12271	1			T2	25		T3	7		T13	3
valid_sources[0x33]	35747	1			T2	22		T3	10		T16	12
valid_sources[0x34]	12372	1			T2	19		T3	1		T41	5
valid_sources[0x35]	14529	1			T2	21		T3	4		T16	13
valid_sources[0x36]	15142	1			T2	47		T3	8		T12	26
valid_sources[0x37]	12605	1			T2	19		T3	5		T16	4
valid_sources[0x38]	12394	1			T2	20		T16	28		T41	5
valid_sources[0x39]	39678	1			T2	10		T3	3		T16	1
valid_sources[0x3a]	14092	1			T2	11		T3	2		T16	3
valid_sources[0x3b]	12001	1			T2	19		T3	6		T13	2
valid_sources[0x3c]	13473	1			T2	11		T3	12		T12	30
valid_sources[0x3d]	13868	1			T2	20		T3	6		T12	20
valid_sources[0x3e]	12205	1			T2	6		T16	20		T41	2
valid_sources[0x3f]	12104	1			T2	26		T16	15		T41	7
valid_sources[0x40]	12301	1			T2	34		T3	4		T16	7
valid_sources[0x41]	12303	1			T2	5		T3	9		T13	1
valid_sources[0x42]	12309	1			T2	17		T3	1		T13	2
valid_sources[0x43]	12131	1			T2	12		T3	1		T16	11
valid_sources[0x44]	12264	1			T2	19		T3	5		T41	7
valid_sources[0x45]	11958	1			T2	29		T3	3		T16	17
valid_sources[0x46]	12903	1			T2	14		T3	3		T16	7
valid_sources[0x47]	11903	1			T2	22		T3	3		T11	1
valid_sources[0x48]	18886	1			T2	18		T3	10		T41	2
valid_sources[0x49]	12698	1			T2	22		T3	1		T16	1
valid_sources[0x4a]	12418	1			T2	11		T3	9		T22	3
valid_sources[0x4b]	12285	1			T2	29		T3	1		T16	14
valid_sources[0x4c]	12154	1			T2	19		T3	16		T41	6
valid_sources[0x4d]	13529	1			T2	41		T3	4		T16	2
valid_sources[0x4e]	12329	1			T2	9		T3	1		T41	6
valid_sources[0x4f]	13163	1			T2	19		T3	2		T12	12
valid_sources[0x50]	12222	1			T2	16		T3	9		T22	1
valid_sources[0x51]	13828	1			T2	7		T3	1		T16	7
valid_sources[0x52]	13469	1			T2	19		T3	7		T12	48
valid_sources[0x53]	11700	1			T2	3		T3	12		T16	2
valid_sources[0x54]	12243	1			T2	23		T3	6		T16	36
valid_sources[0x55]	12366	1			T2	22		T3	3		T22	1
valid_sources[0x56]	19366	1			T2	10		T16	9		T41	4
valid_sources[0x57]	19974	1			T2	41		T3	8		T16	5
valid_sources[0x58]	17643	1			T2	44		T3	8		T41	7
valid_sources[0x59]	14296	1			T2	50		T3	1		T41	5
valid_sources[0x5a]	12901	1			T2	24		T3	11		T16	12
valid_sources[0x5b]	12523	1			T2	3		T3	1		T41	8
valid_sources[0x5c]	12234	1			T2	28		T3	7		T16	18
valid_sources[0x5d]	16067	1			T1	805		T2	13		T3	3
valid_sources[0x5e]	12290	1			T2	22		T3	4		T16	17
valid_sources[0x5f]	13316	1			T2	19		T3	11		T13	1
valid_sources[0x60]	13158	1			T2	14		T16	25		T41	8
valid_sources[0x61]	12235	1			T2	28		T3	11		T16	3
valid_sources[0x62]	12514	1			T2	8		T3	5		T16	2
valid_sources[0x63]	55880	1			T2	16		T3	5		T41	5
valid_sources[0x64]	12308	1			T2	55		T3	10		T16	7
valid_sources[0x65]	12780	1			T2	22		T3	8		T41	6
valid_sources[0x66]	15321	1			T2	23		T16	9		T41	5
valid_sources[0x67]	12213	1			T2	31		T3	3		T41	4
valid_sources[0x68]	12403	1			T2	53		T16	2		T41	5
valid_sources[0x69]	12269	1			T2	7		T16	18		T41	11
valid_sources[0x6a]	13352	1			T2	28		T3	2		T16	17
valid_sources[0x6b]	13010	1			T2	5		T3	3		T12	3
valid_sources[0x6c]	12402	1			T2	49		T3	3		T16	23
valid_sources[0x6d]	13058	1			T2	6		T3	16		T16	16
valid_sources[0x6e]	12086	1			T2	15		T3	6		T16	43
valid_sources[0x6f]	12805	1			T2	15		T3	4		T41	3
valid_sources[0x70]	12389	1			T2	27		T3	1		T12	18
valid_sources[0x71]	12447	1			T2	25		T3	3		T16	2
valid_sources[0x72]	78522	1			T2	22		T3	1		T16	8
valid_sources[0x73]	12130	1			T2	46		T3	4		T41	5
valid_sources[0x74]	16602	1			T2	22		T3	2		T16	7
valid_sources[0x75]	12308	1			T2	19		T3	4		T12	11
valid_sources[0x76]	11837	1			T2	21		T3	3		T16	3
valid_sources[0x77]	12733	1			T2	24		T3	7		T12	31
valid_sources[0x78]	12428	1			T2	13		T3	3		T12	16
valid_sources[0x79]	15926	1			T2	13		T3	4		T16	8
valid_sources[0x7a]	12730	1			T2	58		T3	4		T16	17
valid_sources[0x7b]	11893	1			T2	41		T3	1		T41	19
valid_sources[0x7c]	12400	1			T2	33		T12	14		T16	1
valid_sources[0x7d]	12180	1			T2	47		T3	1		T41	7
valid_sources[0x7e]	12307	1			T2	38		T3	3		T16	8
valid_sources[0x7f]	12452	1			T2	32		T3	10		T41	4
valid_sources[0x80]	12443	1			T2	33		T16	16		T41	10

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1786175

1

T1

156

T2

2806

T3

204

values[0x0]

all_enables

biggest_size

150427

1

T1

179

T2

299

T3

217

values[0x1]

all_enables

biggest_size

148822

1

T1

161

T2

296

T3

212