Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	108736551	15660	0	0
claim_transition_if_regwen_rd_A	108736551	1622	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108736551	15660	0	0
T45	37958	0	0	0
T46	288581	0	0	0
T47	0	5	0	0
T49	0	2	0	0
T60	120301	7	0	0
T61	624702	17	0	0
T65	7672	0	0	0
T97	0	16	0	0
T136	0	7	0	0
T137	0	3	0	0
T138	0	1	0	0
T139	0	2	0	0
T140	0	5	0	0
T141	18595	0	0	0
T142	1715	0	0	0
T143	19533	0	0	0
T144	7516	0	0	0
T145	2275	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	108736551	1622	0	0
T23	28267	0	0	0
T49	112117	3	0	0
T51	606247	0	0	0
T99	0	8	0	0
T104	0	44	0	0
T120	0	15	0	0
T137	0	10	0	0
T138	0	7	0	0
T139	0	1	0	0
T146	0	5	0	0
T147	0	10	0	0
T148	0	55	0	0
T149	20409	0	0	0
T150	16195	0	0	0
T151	10505	0	0	0
T152	1998	0	0	0
T153	27706	0	0	0
T154	6895	0	0	0
T155	701176	0	0	0