Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1545572	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1754779

1

T1

873

T3

1653

T11

620

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	2972308	1			T1	701		T3	3139		T11	334
values[0x0]	163658	1			T1	313		T3	83		T11	274
values[0x1]	164385	1			T1	327		T3	68		T11	254

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1227197	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

2073154

1

T1

990

T3

1988

T11

691

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	10473	1			T1	2		T11	4		T16	23
valid_sources[0x01]	10601	1			T1	5		T11	7		T12	28
valid_sources[0x02]	11614	1			T1	7		T11	4		T12	29
valid_sources[0x03]	12354	1			T1	8		T11	6		T12	4
valid_sources[0x04]	10499	1			T1	5		T11	1		T14	2
valid_sources[0x05]	19182	1			T1	5		T11	9		T14	2
valid_sources[0x06]	62209	1			T11	8		T14	9		T17	1
valid_sources[0x07]	10140	1			T1	4		T11	1		T12	10
valid_sources[0x08]	9993	1			T1	6		T11	3		T12	8
valid_sources[0x09]	11460	1			T1	10		T11	3		T13	1
valid_sources[0x0a]	11251	1			T11	4		T14	6		T16	23
valid_sources[0x0b]	10260	1			T1	4		T11	6		T14	4
valid_sources[0x0c]	10578	1			T1	9		T11	5		T12	13
valid_sources[0x0d]	11723	1			T1	3		T12	18		T17	6
valid_sources[0x0e]	10085	1			T1	2		T17	7		T72	6
valid_sources[0x0f]	10134	1			T1	11		T11	4		T14	1
valid_sources[0x10]	11086	1			T1	1		T11	1		T14	4
valid_sources[0x11]	10139	1			T1	5		T11	13		T16	20
valid_sources[0x12]	10176	1			T1	9		T11	2		T12	15
valid_sources[0x13]	10251	1			T1	2		T12	3		T13	2
valid_sources[0x14]	10365	1			T1	4		T11	4		T13	3
valid_sources[0x15]	10060	1			T1	4		T11	2		T14	2
valid_sources[0x16]	14275	1			T1	7		T14	1		T49	2
valid_sources[0x17]	10235	1			T1	3		T11	4		T14	5
valid_sources[0x18]	10684	1			T1	6		T17	1		T49	6
valid_sources[0x19]	10108	1			T1	5		T11	6		T17	5
valid_sources[0x1a]	10522	1			T1	4		T11	2		T12	5
valid_sources[0x1b]	10200	1			T1	1		T11	3		T12	8
valid_sources[0x1c]	14440	1			T11	8		T14	6		T16	19
valid_sources[0x1d]	10367	1			T1	5		T11	8		T12	39
valid_sources[0x1e]	10606	1			T1	16		T11	14		T17	3
valid_sources[0x1f]	11017	1			T1	2		T11	4		T12	12
valid_sources[0x20]	12012	1			T1	2		T14	3		T17	1
valid_sources[0x21]	11856	1			T1	7		T17	3		T49	1
valid_sources[0x22]	10098	1			T1	8		T11	1		T13	1
valid_sources[0x23]	12140	1			T1	9		T11	3		T14	3
valid_sources[0x24]	10233	1			T1	8		T11	11		T12	26
valid_sources[0x25]	10721	1			T1	3		T11	7		T13	1
valid_sources[0x26]	10053	1			T1	4		T3	17		T16	30
valid_sources[0x27]	17769	1			T1	4		T11	3		T17	7
valid_sources[0x28]	10272	1			T1	4		T11	3		T12	5
valid_sources[0x29]	10397	1			T1	5		T11	1		T14	5
valid_sources[0x2a]	10014	1			T1	1		T12	37		T13	1
valid_sources[0x2b]	13635	1			T1	3		T11	3		T17	3
valid_sources[0x2c]	9984	1			T1	15		T11	1		T12	50
valid_sources[0x2d]	10231	1			T1	4		T11	1		T13	1
valid_sources[0x2e]	11626	1			T1	6		T11	2		T14	21
valid_sources[0x2f]	10722	1			T1	4		T14	3		T17	11
valid_sources[0x30]	10240	1			T1	10		T11	7		T14	2
valid_sources[0x31]	10174	1			T1	6		T11	10		T14	6
valid_sources[0x32]	12668	1			T1	6		T11	3		T13	1
valid_sources[0x33]	11661	1			T1	3		T11	2		T12	51
valid_sources[0x34]	13670	1			T1	8		T11	11		T13	1
valid_sources[0x35]	10362	1			T1	2		T11	4		T16	6
valid_sources[0x36]	19907	1			T1	2		T12	13		T14	1
valid_sources[0x37]	10129	1			T1	4		T11	4		T12	11
valid_sources[0x38]	10451	1			T1	8		T13	2		T17	19
valid_sources[0x39]	16635	1			T1	8		T11	6		T13	2
valid_sources[0x3a]	10401	1			T1	5		T11	2		T14	1
valid_sources[0x3b]	14848	1			T1	4		T12	24		T14	2
valid_sources[0x3c]	10348	1			T1	4		T11	11		T12	56
valid_sources[0x3d]	10261	1			T1	4		T11	3		T12	2
valid_sources[0x3e]	10149	1			T12	6		T14	1		T17	6
valid_sources[0x3f]	30027	1			T1	6		T11	2		T12	4
valid_sources[0x40]	10064	1			T1	3		T11	8		T12	11
valid_sources[0x41]	10443	1			T1	11		T12	1		T13	1
valid_sources[0x42]	10579	1			T1	4		T11	7		T12	2
valid_sources[0x43]	10222	1			T1	5		T11	3		T12	11
valid_sources[0x44]	10117	1			T1	12		T11	3		T12	8
valid_sources[0x45]	9924	1			T1	7		T3	17		T11	1
valid_sources[0x46]	10301	1			T1	9		T11	3		T13	1
valid_sources[0x47]	11415	1			T1	10		T11	1		T12	11
valid_sources[0x48]	10397	1			T1	1		T3	17		T11	7
valid_sources[0x49]	10530	1			T1	7		T11	8		T17	9
valid_sources[0x4a]	15339	1			T1	3		T11	5		T17	1
valid_sources[0x4b]	14669	1			T1	5		T11	3		T14	3
valid_sources[0x4c]	102721	1			T1	3		T11	2		T12	5
valid_sources[0x4d]	12084	1			T1	8		T11	1		T17	7
valid_sources[0x4e]	10481	1			T1	2		T14	1		T15	26
valid_sources[0x4f]	11281	1			T1	4		T11	4		T13	1
valid_sources[0x50]	10171	1			T1	8		T11	2		T13	1
valid_sources[0x51]	10803	1			T1	4		T11	1		T12	3
valid_sources[0x52]	10207	1			T1	6		T13	2		T14	8
valid_sources[0x53]	10275	1			T1	9		T11	8		T12	33
valid_sources[0x54]	18573	1			T1	14		T11	1		T12	6
valid_sources[0x55]	13309	1			T1	4		T3	3137		T11	5
valid_sources[0x56]	10603	1			T1	11		T11	4		T14	5
valid_sources[0x57]	10185	1			T11	5		T14	8		T15	9
valid_sources[0x58]	12160	1			T1	5		T11	2		T12	10
valid_sources[0x59]	9999	1			T1	3		T11	8		T14	16
valid_sources[0x5a]	10036	1			T1	3		T11	2		T17	3
valid_sources[0x5b]	10484	1			T1	5		T11	1		T14	1
valid_sources[0x5c]	10185	1			T1	6		T11	5		T12	6
valid_sources[0x5d]	20619	1			T1	7		T11	3		T14	4
valid_sources[0x5e]	10318	1			T1	11		T11	1		T12	18
valid_sources[0x5f]	12254	1			T1	4		T11	5		T12	9
valid_sources[0x60]	11561	1			T1	1		T12	1		T14	13
valid_sources[0x61]	10722	1			T1	7		T11	10		T14	1
valid_sources[0x62]	11529	1			T1	8		T11	1		T14	7
valid_sources[0x63]	10298	1			T1	5		T11	11		T16	4
valid_sources[0x64]	12232	1			T1	5		T3	17		T11	1
valid_sources[0x65]	10176	1			T1	6		T11	8		T13	1
valid_sources[0x66]	9838	1			T1	4		T14	3		T17	3
valid_sources[0x67]	10136	1			T1	2		T11	1		T17	5
valid_sources[0x68]	9831	1			T1	2		T14	7		T15	15
valid_sources[0x69]	10458	1			T11	2		T12	69		T17	7
valid_sources[0x6a]	10113	1			T1	8		T11	6		T16	47
valid_sources[0x6b]	9917	1			T1	2		T11	1		T12	5
valid_sources[0x6c]	10419	1			T1	4		T11	2		T17	4
valid_sources[0x6d]	10245	1			T1	2		T11	1		T14	1
valid_sources[0x6e]	10671	1			T1	6		T11	6		T12	13
valid_sources[0x6f]	33645	1			T1	5		T11	6		T12	19
valid_sources[0x70]	10524	1			T1	3		T11	1		T12	25
valid_sources[0x71]	10090	1			T1	4		T11	2		T12	35
valid_sources[0x72]	10133	1			T1	2		T16	4		T17	7
valid_sources[0x73]	10296	1			T1	3		T11	1		T12	2
valid_sources[0x74]	28884	1			T1	5		T11	2		T12	51
valid_sources[0x75]	10529	1			T1	2		T11	2		T14	9
valid_sources[0x76]	10188	1			T1	13		T11	7		T12	15
valid_sources[0x77]	10505	1			T11	2		T14	2		T17	5
valid_sources[0x78]	10214	1			T1	6		T11	3		T17	5
valid_sources[0x79]	10417	1			T1	9		T11	1		T14	9
valid_sources[0x7a]	10538	1			T1	4		T11	1		T16	43
valid_sources[0x7b]	12157	1			T1	10		T11	4		T12	13
valid_sources[0x7c]	10320	1			T1	10		T11	3		T17	2
valid_sources[0x7d]	13024	1			T1	1		T11	1		T12	3
valid_sources[0x7e]	16178	1			T1	4		T11	3		T12	2
valid_sources[0x7f]	10131	1			T1	1		T11	1		T14	4
valid_sources[0x80]	10069	1			T1	10		T11	7		T13	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1472391

1

T1

320

T3

1523

T11

163

values[0x0]

all_enables

biggest_size

141697

1

T1

270

T3

71

T11

242

values[0x1]

all_enables

biggest_size

140691

1

T1

283

T3

59

T11

215