SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
tb.dut.u_prim_lc_sync | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack | 100.00 | 100.00 | 100.00 | ||||
tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
93.47 | 100.00 | 83.10 | 99.89 | 100.00 | 84.38 | dut |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.77 | 98.87 | 93.02 | 100.00 | 98.63 | 93.33 | u_lc_ctrl_fsm |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.77 | 98.87 | 93.02 | 100.00 | 98.63 | 93.33 | u_lc_ctrl_fsm |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.77 | 98.87 | 93.02 | 100.00 | 98.63 | 93.33 | u_lc_ctrl_fsm |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[1].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[2].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[3].gen_bits[3].u_prim_buf | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.77 | 98.87 | 93.02 | 100.00 | 98.63 | 93.33 | u_lc_ctrl_fsm |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.77 | 98.87 | 93.02 | 100.00 | 98.63 | 93.33 | u_lc_ctrl_fsm |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
100.00 | 100.00 | 100.00 | 100.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | NAME |
96.77 | 98.87 | 93.02 | 100.00 | 98.63 | 93.33 | u_lc_ctrl_fsm |
NAME | SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT |
gen_buffs[0].gen_bits[0].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[1].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[2].u_prim_buf | 100.00 | 100.00 | |||||
gen_buffs[0].gen_bits[3].u_prim_buf | 100.00 | 100.00 | |||||
gen_flops.u_prim_flop_2sync | 100.00 | 100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 4 | 4 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 3 | 3 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 4 | 4 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 9 | 9 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 8 | 8 |
SCORE | LINE |
100.00 | 100.00 |
SCORE | LINE |
100.00 | 100.00 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 4 | 4 | 100.00 | 4 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 4 | 4 | 100.00 | 4 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 5705 | 5705 | 0 | 0 |
OutputsKnown_A | 648222233 | 620752255 | 0 | 0 |
gen_flops.OutputDelay_A | 277715102 | 265498595 | 0 | 7239 |
gen_no_flops.OutputDelay_A | 370507131 | 354783632 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 5705 | 5705 | 0 | 0 |
T1 | 7 | 7 | 0 | 0 |
T2 | 7 | 7 | 0 | 0 |
T3 | 7 | 7 | 0 | 0 |
T4 | 7 | 7 | 0 | 0 |
T11 | 7 | 7 | 0 | 0 |
T12 | 7 | 7 | 0 | 0 |
T13 | 7 | 7 | 0 | 0 |
T14 | 7 | 7 | 0 | 0 |
T15 | 7 | 7 | 0 | 0 |
T16 | 7 | 7 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 648222233 | 620752255 | 0 | 0 |
T1 | 177464 | 141398 | 0 | 0 |
T2 | 818993 | 776034 | 0 | 0 |
T3 | 249949 | 244832 | 0 | 0 |
T4 | 527086 | 523950 | 0 | 0 |
T11 | 140182 | 103411 | 0 | 0 |
T12 | 261415 | 212877 | 0 | 0 |
T13 | 15183 | 14553 | 0 | 0 |
T14 | 161301 | 130956 | 0 | 0 |
T15 | 180047 | 149317 | 0 | 0 |
T16 | 191520 | 160965 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 277715102 | 265498595 | 0 | 7239 |
T1 | 75234 | 59378 | 0 | 9 |
T2 | 350997 | 331848 | 0 | 9 |
T3 | 107121 | 104847 | 0 | 9 |
T4 | 225894 | 224496 | 0 | 9 |
T11 | 60078 | 43716 | 0 | 9 |
T12 | 112035 | 90405 | 0 | 9 |
T13 | 6507 | 6228 | 0 | 9 |
T14 | 69129 | 55629 | 0 | 9 |
T15 | 77163 | 63471 | 0 | 9 |
T16 | 82080 | 68463 | 0 | 9 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 370507131 | 354783632 | 0 | 0 |
T1 | 102230 | 81411 | 0 | 0 |
T2 | 467996 | 443448 | 0 | 0 |
T3 | 142828 | 139904 | 0 | 0 |
T4 | 301192 | 299400 | 0 | 0 |
T11 | 80104 | 59092 | 0 | 0 |
T12 | 149380 | 121644 | 0 | 0 |
T13 | 8676 | 8316 | 0 | 0 |
T14 | 92172 | 74832 | 0 | 0 |
T15 | 102884 | 85324 | 0 | 0 |
T16 | 109440 | 91980 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 3 | 3 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 2 | 2 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 815 | 815 | 0 | 0 |
OutputsKnown_A | 92906207 | 88932821 | 0 | 0 |
gen_no_flops.OutputDelay_A | 92906207 | 88932821 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 815 | 815 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92906207 | 88932821 | 0 | 0 |
T1 | 30040 | 23890 | 0 | 0 |
T2 | 116999 | 110862 | 0 | 0 |
T3 | 35707 | 34976 | 0 | 0 |
T4 | 75298 | 74850 | 0 | 0 |
T11 | 20026 | 14773 | 0 | 0 |
T12 | 37345 | 30411 | 0 | 0 |
T13 | 2169 | 2079 | 0 | 0 |
T14 | 23043 | 18708 | 0 | 0 |
T15 | 25721 | 21331 | 0 | 0 |
T16 | 27360 | 22995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92906207 | 88932821 | 0 | 0 |
T1 | 30040 | 23890 | 0 | 0 |
T2 | 116999 | 110862 | 0 | 0 |
T3 | 35707 | 34976 | 0 | 0 |
T4 | 75298 | 74850 | 0 | 0 |
T11 | 20026 | 14773 | 0 | 0 |
T12 | 37345 | 30411 | 0 | 0 |
T13 | 2169 | 2079 | 0 | 0 |
T14 | 23043 | 18708 | 0 | 0 |
T15 | 25721 | 21331 | 0 | 0 |
T16 | 27360 | 22995 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 815 | 815 | 0 | 0 |
OutputsKnown_A | 92592094 | 88679637 | 0 | 0 |
gen_flops.OutputDelay_A | 92592094 | 88523097 | 0 | 2391 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 815 | 815 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92592094 | 88679637 | 0 | 0 |
T1 | 24082 | 19113 | 0 | 0 |
T2 | 116999 | 110862 | 0 | 0 |
T3 | 35707 | 34976 | 0 | 0 |
T4 | 75298 | 74850 | 0 | 0 |
T11 | 20026 | 14773 | 0 | 0 |
T12 | 37345 | 30411 | 0 | 0 |
T13 | 2169 | 2079 | 0 | 0 |
T14 | 23043 | 18708 | 0 | 0 |
T15 | 25721 | 21331 | 0 | 0 |
T16 | 27360 | 22995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92592094 | 88523097 | 0 | 2391 |
T1 | 24082 | 18918 | 0 | 3 |
T2 | 116999 | 110616 | 0 | 3 |
T3 | 35707 | 34949 | 0 | 3 |
T4 | 75298 | 74832 | 0 | 3 |
T11 | 20026 | 14572 | 0 | 3 |
T12 | 37345 | 30135 | 0 | 3 |
T13 | 2169 | 2076 | 0 | 3 |
T14 | 23043 | 18543 | 0 | 3 |
T15 | 25721 | 21157 | 0 | 3 |
T16 | 27360 | 22821 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 4 | 4 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 3 | 3 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 815 | 815 | 0 | 0 |
OutputsKnown_A | 92561504 | 88644493 | 0 | 0 |
gen_no_flops.OutputDelay_A | 92561504 | 88644493 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 815 | 815 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92561504 | 88644493 | 0 | 0 |
T1 | 25576 | 20437 | 0 | 0 |
T2 | 116999 | 110862 | 0 | 0 |
T3 | 35707 | 34976 | 0 | 0 |
T4 | 75298 | 74850 | 0 | 0 |
T11 | 20026 | 14773 | 0 | 0 |
T12 | 37345 | 30411 | 0 | 0 |
T13 | 2169 | 2079 | 0 | 0 |
T14 | 23043 | 18708 | 0 | 0 |
T15 | 25721 | 21331 | 0 | 0 |
T16 | 27360 | 22995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92561504 | 88644493 | 0 | 0 |
T1 | 25576 | 20437 | 0 | 0 |
T2 | 116999 | 110862 | 0 | 0 |
T3 | 35707 | 34976 | 0 | 0 |
T4 | 75298 | 74850 | 0 | 0 |
T11 | 20026 | 14773 | 0 | 0 |
T12 | 37345 | 30411 | 0 | 0 |
T13 | 2169 | 2079 | 0 | 0 |
T14 | 23043 | 18708 | 0 | 0 |
T15 | 25721 | 21331 | 0 | 0 |
T16 | 27360 | 22995 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 5 | 5 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 4 | 4 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 815 | 815 | 0 | 0 |
OutputsKnown_A | 92517596 | 88600252 | 0 | 0 |
gen_no_flops.OutputDelay_A | 92517596 | 88600252 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 815 | 815 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92517596 | 88600252 | 0 | 0 |
T1 | 24364 | 19340 | 0 | 0 |
T2 | 116999 | 110862 | 0 | 0 |
T3 | 35707 | 34976 | 0 | 0 |
T4 | 75298 | 74850 | 0 | 0 |
T11 | 20026 | 14773 | 0 | 0 |
T12 | 37345 | 30411 | 0 | 0 |
T13 | 2169 | 2079 | 0 | 0 |
T14 | 23043 | 18708 | 0 | 0 |
T15 | 25721 | 21331 | 0 | 0 |
T16 | 27360 | 22995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92517596 | 88600252 | 0 | 0 |
T1 | 24364 | 19340 | 0 | 0 |
T2 | 116999 | 110862 | 0 | 0 |
T3 | 35707 | 34976 | 0 | 0 |
T4 | 75298 | 74850 | 0 | 0 |
T11 | 20026 | 14773 | 0 | 0 |
T12 | 37345 | 30411 | 0 | 0 |
T13 | 2169 | 2079 | 0 | 0 |
T14 | 23043 | 18708 | 0 | 0 |
T15 | 25721 | 21331 | 0 | 0 |
T16 | 27360 | 22995 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 9 | 9 | 100.00 | |
ALWAYS | 84 | 0 | 0 | |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
84 | unreachable | ||
85 | unreachable | ||
87 | unreachable | ||
93 | 1 | 1 | |
106 | 8 | 8 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 815 | 815 | 0 | 0 |
OutputsKnown_A | 92521824 | 88606066 | 0 | 0 |
gen_no_flops.OutputDelay_A | 92521824 | 88606066 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 815 | 815 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92521824 | 88606066 | 0 | 0 |
T1 | 22250 | 17744 | 0 | 0 |
T2 | 116999 | 110862 | 0 | 0 |
T3 | 35707 | 34976 | 0 | 0 |
T4 | 75298 | 74850 | 0 | 0 |
T11 | 20026 | 14773 | 0 | 0 |
T12 | 37345 | 30411 | 0 | 0 |
T13 | 2169 | 2079 | 0 | 0 |
T14 | 23043 | 18708 | 0 | 0 |
T15 | 25721 | 21331 | 0 | 0 |
T16 | 27360 | 22995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92521824 | 88606066 | 0 | 0 |
T1 | 22250 | 17744 | 0 | 0 |
T2 | 116999 | 110862 | 0 | 0 |
T3 | 35707 | 34976 | 0 | 0 |
T4 | 75298 | 74850 | 0 | 0 |
T11 | 20026 | 14773 | 0 | 0 |
T12 | 37345 | 30411 | 0 | 0 |
T13 | 2169 | 2079 | 0 | 0 |
T14 | 23043 | 18708 | 0 | 0 |
T15 | 25721 | 21331 | 0 | 0 |
T16 | 27360 | 22995 | 0 | 0 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 815 | 815 | 0 | 0 |
OutputsKnown_A | 92561504 | 88644493 | 0 | 0 |
gen_flops.OutputDelay_A | 92561504 | 88487749 | 0 | 2424 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 815 | 815 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92561504 | 88644493 | 0 | 0 |
T1 | 25576 | 20437 | 0 | 0 |
T2 | 116999 | 110862 | 0 | 0 |
T3 | 35707 | 34976 | 0 | 0 |
T4 | 75298 | 74850 | 0 | 0 |
T11 | 20026 | 14773 | 0 | 0 |
T12 | 37345 | 30411 | 0 | 0 |
T13 | 2169 | 2079 | 0 | 0 |
T14 | 23043 | 18708 | 0 | 0 |
T15 | 25721 | 21331 | 0 | 0 |
T16 | 27360 | 22995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92561504 | 88487749 | 0 | 2424 |
T1 | 25576 | 20230 | 0 | 3 |
T2 | 116999 | 110616 | 0 | 3 |
T3 | 35707 | 34949 | 0 | 3 |
T4 | 75298 | 74832 | 0 | 3 |
T11 | 20026 | 14572 | 0 | 3 |
T12 | 37345 | 30135 | 0 | 3 |
T13 | 2169 | 2076 | 0 | 3 |
T14 | 23043 | 18543 | 0 | 3 |
T15 | 25721 | 21157 | 0 | 3 |
T16 | 27360 | 22821 | 0 | 3 |
Line No. | Total | Covered | Percent | |
---|---|---|---|---|
TOTAL | 2 | 2 | 100.00 | |
ALWAYS | 68 | 1 | 1 | 100.00 |
CONT_ASSIGN | 106 | 1 | 1 | 100.00 |
Line No. | Covered | Statements | |
---|---|---|---|
68 | 1 | 1 | |
106 | 1 | 1 |
Total | Attempted | Percent | Succeeded/Matched | Percent | |
---|---|---|---|---|---|
Assertions | 3 | 3 | 100.00 | 3 | 100.00 |
Cover properties | 0 | 0 | 0 | ||
Cover sequences | 0 | 0 | 0 | ||
Total | 3 | 3 | 100.00 | 3 | 100.00 |
Name | Attempts | Real Successes | Failures | Incomplete |
NumCopiesMustBeGreaterZero_A | 815 | 815 | 0 | 0 |
OutputsKnown_A | 92561504 | 88644493 | 0 | 0 |
gen_flops.OutputDelay_A | 92561504 | 88487749 | 0 | 2424 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 815 | 815 | 0 | 0 |
T1 | 1 | 1 | 0 | 0 |
T2 | 1 | 1 | 0 | 0 |
T3 | 1 | 1 | 0 | 0 |
T4 | 1 | 1 | 0 | 0 |
T11 | 1 | 1 | 0 | 0 |
T12 | 1 | 1 | 0 | 0 |
T13 | 1 | 1 | 0 | 0 |
T14 | 1 | 1 | 0 | 0 |
T15 | 1 | 1 | 0 | 0 |
T16 | 1 | 1 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92561504 | 88644493 | 0 | 0 |
T1 | 25576 | 20437 | 0 | 0 |
T2 | 116999 | 110862 | 0 | 0 |
T3 | 35707 | 34976 | 0 | 0 |
T4 | 75298 | 74850 | 0 | 0 |
T11 | 20026 | 14773 | 0 | 0 |
T12 | 37345 | 30411 | 0 | 0 |
T13 | 2169 | 2079 | 0 | 0 |
T14 | 23043 | 18708 | 0 | 0 |
T15 | 25721 | 21331 | 0 | 0 |
T16 | 27360 | 22995 | 0 | 0 |
Name | Attempts | Real Successes | Failures | Incomplete |
---|---|---|---|---|
Total | 92561504 | 88487749 | 0 | 2424 |
T1 | 25576 | 20230 | 0 | 3 |
T2 | 116999 | 110616 | 0 | 3 |
T3 | 35707 | 34949 | 0 | 3 |
T4 | 75298 | 74832 | 0 | 3 |
T11 | 20026 | 14572 | 0 | 3 |
T12 | 37345 | 30135 | 0 | 3 |
T13 | 2169 | 2076 | 0 | 3 |
T14 | 23043 | 18543 | 0 | 3 |
T15 | 25721 | 21157 | 0 | 3 |
T16 | 27360 | 22821 | 0 | 3 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |