Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	95049363	13904	0	0
claim_transition_if_regwen_rd_A	95049363	1339	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95049363	13904	0	0
T19	132826	5	0	0
T20	341125	0	0	0
T21	216800	0	0	0
T22	203127	6	0	0
T37	0	3	0	0
T46	41117	0	0	0
T47	34821	0	0	0
T50	22754	0	0	0
T69	6051	0	0	0
T80	28094	0	0	0
T81	5687	0	0	0
T96	0	1	0	0
T138	0	1	0	0
T139	0	5	0	0
T140	0	2	0	0
T141	0	12	0	0
T142	0	1	0	0
T143	0	1	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	95049363	1339	0	0
T41	788	0	0	0
T62	32412	0	0	0
T96	167476	3	0	0
T107	0	60	0	0
T119	0	1	0	0
T120	0	20	0	0
T138	0	4	0	0
T140	0	7	0	0
T143	0	2	0	0
T144	0	18	0	0
T145	0	7	0	0
T146	0	9	0	0
T147	886	0	0	0
T148	25289	0	0	0
T149	7700	0	0	0
T150	51138	0	0	0
T151	1514	0	0	0
T152	5165	0	0	0
T153	22133	0	0	0