Unified Coverage Report :: Group :: tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

Group : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
12.90	1	100	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

---

Summary for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	54	10	15.62
Crosses	60	54	6	10.00

Variables for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_scrap_state0_i_cp	2	1	1	50.00	100	1	1	2
esc_scrap_state1_i_cp	2	1	1	50.00	100	1	1	2
fsm_state_q	15	12	3	20.00	100	1	1	0
fsm_state_q_cp	45	40	5	11.11	100	1	1	0

Crosses for Group tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if::lc_ctrl_fsm_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
scrap_state0_xp	30	27	3	10.00	100	1	1	0
scrap_state1_xp	30	27	3	10.00	100	1	1	0

Summary for Variable esc_scrap_state0_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for esc_scrap_state0_i_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2212661

1

T1

2140

T2

1530

T3

2862

---

Summary for Variable esc_scrap_state1_i_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	1	1	50.00

Automatically Generated Bins for esc_scrap_state1_i_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2212661

1

T1

2140

T2

1530

T3

2862

---

Summary for Variable fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	15	12	3	20.00

Automatically Generated Bins for fsm_state_q

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[ClkMuxSt]	0	1	1
auto[CntIncrSt]	0	1	1
auto[CntProgSt]	0	1	1
auto[TransCheckSt]	0	1	1
auto[TokenHashSt]	0	1	1
auto[FlashRmaSt]	0	1	1
auto[TokenCheck0St]	0	1	1
auto[TokenCheck1St]	0	1	1
auto[TransProgSt]	0	1	1
auto[PostTransSt]	0	1	1
auto[EscalateSt]	0	1	1
auto[InvalidSt]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ResetSt]	50013	1			T1	182		T2	96		T3	100
auto[IdleSt]	2133181	1			T1	1958		T2	1434		T3	2762
auto[ScrapSt]	29467	1			T19	1443		T16	342		T17	470

---

Summary for Variable fsm_state_q_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	45	40	5	11.11

User Defined Bins for fsm_state_q_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
InvalidSt	0	1	1
EscalateSt	0	1	1
PostTransSt	0	1	1
TransProgSt	0	1	1
TokenCheck1St	0	1	1
TokenCheck0St	0	1	1
FlashRmaSt	0	1	1
TokenHashSt	0	1	1
TransCheckSt	0	1	1
CntProgSt	0	1	1
CntIncrSt	0	1	1
ClkMuxSt	0	1	1
arcs[IdleSt=>ClkMuxSt]	0	1	1
arcs[ClkMuxSt=>CntIncrSt]	0	1	1
arcs[CntIncrSt=>PostTransSt]	0	1	1
arcs[CntIncrSt=>CntProgSt]	0	1	1
arcs[CntProgSt=>PostTransSt]	0	1	1
arcs[CntProgSt=>TransCheckSt]	0	1	1
arcs[TransCheckSt=>PostTransSt]	0	1	1
arcs[TransCheckSt=>TokenHashSt]	0	1	1
arcs[TokenHashSt=>PostTransSt]	0	1	1
arcs[TokenHashSt=>FlashRmaSt]	0	1	1
arcs[FlashRmaSt=>TokenCheck0St]	0	1	1
arcs[TokenCheck0St=>PostTransSt]	0	1	1
arcs[TokenCheck0St=>TokenCheck1St]	0	1	1
arcs[TokenCheck1St=>PostTransSt]	0	1	1
arcs[TokenCheck1St=>TokenCheck1St]	0	1	1
arcs[TransProgSt=>PostTransSt]	0	1	1
arcs[IdleSt=>EscalateSt]	0	1	1
arcs[ClkMuxSt=>EscalateSt]	0	1	1
arcs[CntIncrSt=>EscalateSt]	0	1	1
arcs[CntProgSt=>EscalateSt]	0	1	1
arcs[TransCheckSt=>EscalateSt]	0	1	1
arcs[TokenHashSt=>EscalateSt]	0	1	1
arcs[FlashRmaSt=>EscalateSt]	0	1	1
arcs[TokenCheck0St=>EscalateSt]	0	1	1
arcs[TokenCheck1St=>EscalateSt]	0	1	1
arcs[TransProgSt=>EscalateSt]	0	1	1
arcs[PostTransSt=>EscalateSt]	0	1	1
arcs[InvalidSt=>EscalateSt]	0	1	1

Excluded/Illegal bins

NAME	COUNT	STATUS
IllegalEncoding	0	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
ScrapSt	29467	1			T19	1443		T16	342		T17	470
IdleSt	2133181	1			T1	1958		T2	1434		T3	2762
ResetSt	50013	1			T1	182		T2	96		T3	100
arcs[ResetSt=>IdleSt]	576	1			T1	2		T2	1		T3	1
arcs[IdleSt=>ScrapSt]	37	1			T19	2		T16	2		T17	2

---

Summary for Cross scrap_state0_xp

Samples crossed: esc_scrap_state0_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	27	3	10.00	27

Automatically Generated Cross Bins for scrap_state0_xp

Element holes

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	*	--	--	15

Uncovered bins

esc_scrap_state0_i_cp	fsm_state_q	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[ClkMuxSt] , auto[CntIncrSt] , auto[CntProgSt] , auto[TransCheckSt] , auto[TokenHashSt] , auto[FlashRmaSt] , auto[TokenCheck0St] , auto[TokenCheck1St] , auto[TransProgSt] , auto[PostTransSt]]	--	--	10
[auto[0]]	[auto[EscalateSt] , auto[InvalidSt]]	--	--	2

Covered bins

esc_scrap_state0_i_cp

fsm_state_q

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[ResetSt]

50013

1

T1

182

T2

96

T3

100

auto[0]

auto[IdleSt]

2133181

1

T1

1958

T2

1434

T3

2762

auto[0]

auto[ScrapSt]

29467

1

T19

1443

T16

342

T17

470

---

Summary for Cross scrap_state1_xp

Samples crossed: esc_scrap_state1_i_cp fsm_state_q

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	30	27	3	10.00	27

Automatically Generated Cross Bins for scrap_state1_xp

Element holes

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	*	--	--	15

Uncovered bins

esc_scrap_state1_i_cp	fsm_state_q	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[ClkMuxSt] , auto[CntIncrSt] , auto[CntProgSt] , auto[TransCheckSt] , auto[TokenHashSt] , auto[FlashRmaSt] , auto[TokenCheck0St] , auto[TokenCheck1St] , auto[TransProgSt] , auto[PostTransSt]]	--	--	10
[auto[0]]	[auto[EscalateSt] , auto[InvalidSt]]	--	--	2

Covered bins

esc_scrap_state1_i_cp

fsm_state_q

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[ResetSt]

50013

1

T1

182

T2

96

T3

100

auto[0]

auto[IdleSt]

2133181

1

T1

1958

T2

1434

T3

2762

auto[0]

auto[ScrapSt]

29467

1

T19

1443

T16

342

T17

470