Unified Coverage Report

Total Coverage Summary

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
47.40	45.42	68.50	52.42	0.00	26.76	100.00	38.69

Total tests in report: 185

Tests are in graded order

Scores are accumulated (Total) and incremental (Incr) for each test.

SCORE		LINE		COND		TOGGLE		FSM		BRANCH		ASSERT		GROUP
TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	TOTAL	INCR	NAME
37.33	37.33	42.35	42.35	55.99	55.99	25.34	25.34	0.00	0.00	25.93	25.93	94.55	94.55	17.14	17.14	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3284240315
45.22	7.89	45.02	2.67	64.18	8.19	50.80	25.45	0.00	0.00	26.76	0.83	95.83	1.28	33.92	16.78	/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2693064096
46.71	1.49	45.02	0.00	64.45	0.27	59.74	8.95	0.00	0.00	26.76	0.00	95.83	0.00	35.16	1.24	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1959877781
47.62	0.92	45.42	0.40	65.17	0.72	60.83	1.08	0.00	0.00	26.76	0.00	99.68	3.85	35.51	0.35	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3910665161
48.23	0.61	45.42	0.00	65.80	0.63	61.97	1.15	0.00	0.00	26.76	0.00	99.68	0.00	37.99	2.47	/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.297441383
48.48	0.25	45.42	0.00	65.80	0.00	62.87	0.90	0.00	0.00	26.76	0.00	100.00	0.32	38.52	0.53	/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.280798447
48.61	0.13	45.42	0.00	66.16	0.36	63.44	0.57	0.00	0.00	26.76	0.00	100.00	0.00	38.52	0.00	/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1722068379
48.70	0.09	45.42	0.00	66.61	0.45	63.59	0.15	0.00	0.00	26.76	0.00	100.00	0.00	38.52	0.00	/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.919763778
48.77	0.07	45.42	0.00	67.06	0.45	63.64	0.05	0.00	0.00	26.76	0.00	100.00	0.00	38.52	0.00	/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.995106528
48.83	0.05	45.42	0.00	67.33	0.27	63.75	0.11	0.00	0.00	26.76	0.00	100.00	0.00	38.52	0.00	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.206007399
48.86	0.04	45.42	0.00	67.60	0.27	63.75	0.00	0.00	0.00	26.76	0.00	100.00	0.00	38.52	0.00	/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2678044061
48.90	0.04	45.42	0.00	67.60	0.00	63.82	0.07	0.00	0.00	26.76	0.00	100.00	0.00	38.69	0.18	/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3817755791
48.93	0.03	45.42	0.00	67.78	0.18	63.82	0.00	0.00	0.00	26.76	0.00	100.00	0.00	38.69	0.00	/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2402539381
48.95	0.03	45.42	0.00	67.96	0.18	63.82	0.00	0.00	0.00	26.76	0.00	100.00	0.00	38.69	0.00	/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.107049218
48.98	0.03	45.42	0.00	68.14	0.18	63.82	0.00	0.00	0.00	26.76	0.00	100.00	0.00	38.69	0.00	/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2647633189
48.99	0.01	45.42	0.00	68.23	0.09	63.82	0.00	0.00	0.00	26.76	0.00	100.00	0.00	38.69	0.00	/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.406075271
49.00	0.01	45.42	0.00	68.32	0.09	63.82	0.00	0.00	0.00	26.76	0.00	100.00	0.00	38.69	0.00	/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4201655908
49.02	0.01	45.42	0.00	68.41	0.09	63.82	0.00	0.00	0.00	26.76	0.00	100.00	0.00	38.69	0.00	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2991433819
49.03	0.01	45.42	0.00	68.50	0.09	63.82	0.00	0.00	0.00	26.76	0.00	100.00	0.00	38.69	0.00	/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.118231290
49.03	0.01	45.42	0.00	68.50	0.00	63.85	0.02	0.00	0.00	26.76	0.00	100.00	0.00	38.69	0.00	/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2597218761

Tests that do not contribute to grading

Name
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2273200428
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2796111010
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1123072977
/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.277592045
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2784146174
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.4288636692
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2545171864
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.795857262
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3486103326
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3513258262
/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.631748116
/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3102819030
/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3704166681
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2919666505
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1935880705
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2921390302
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.514500679
/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2939063592
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.575811830
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2530329121
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1266052731
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2489121910
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2767547326
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1288415862
/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2199730907
/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3279154546
/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1758538671
/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2030560589
/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.4217618694
/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.174239613
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4128628810
/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3851826734
/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2984532138
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.984855496
/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1074183057
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2757832869
/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3276155841
/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3918640215
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.57598954
/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3143811145
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1641494972
/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3751803753
/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2660528977
/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1897821478
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2506379068
/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2989147228
/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2583829428
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.251946233
/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3827737181
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.917154562
/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1330268230
/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.947822338
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2061623133
/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1348886736
/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2708935851
/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1961086982
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2697096990
/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2679422816
/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.786317630
/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1265286886
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1372469482
/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2251632789
/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3298626255
/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.180511127
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3065303307
/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1770208276
/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.497496525
/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.399153321
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1581225237
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1689125332
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2298057982
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.142525595
/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.160967517
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1328401409
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2072179927
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4273779329
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2090571709
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.868116959
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1888248237
/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.273542507
/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.265504933
/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.879103475
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2496504764
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.4223370463
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.679956416
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2793943724
/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1250760983
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3645172213
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3665724911
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4086967296
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1257875590
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2702105396
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.980624642
/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3610425519
/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.377476276
/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1124257588
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1040643741
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3325510103
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2370719460
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3203970659
/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2842618873
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1883454153
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.4111421463
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.693332089
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.593835299
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1932051545
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2561042786
/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.762788891
/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2206035315
/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3744796575
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.824723021
/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3489459151
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1141896855
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3730400019
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2276876275
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1352188665
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3998692910
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3947385317
/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2472969688
/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2759435235
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2964546656
/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.594560700
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3080641571
/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3173034764
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.601856027
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2119359262
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1825750268
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1880600501
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1268970450
/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3836857176
/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1694624100
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.320938591
/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2310534129
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.653021698
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.648964587
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1399079663
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3643145982
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1457638299
/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2408261858
/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3058380003
/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3630897474
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.200952504
/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3489570284
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.113673798
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3247051161
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3627409355
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2443614734
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2230037862
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.615653078
/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3839886826
/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1988053899
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.471363698
/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1873679101
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1950151587
/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.453731786
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2900225911
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.907666648
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3947580125
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3464551047
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3602749617
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.141806839
/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3330727611
/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2811074085
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3907881634
/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3394964604

Total test records in report: 185

tests.html | tests1.html | tests2.html

TEST NO	TEST LOCATION	STARTED	FINISHED	SIMULATION TIME
T1	/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.280798447	Aug 14 04:29:50 PM PDT 24	Aug 14 04:29:52 PM PDT 24	21415402 ps
T2	/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2206035315	Aug 14 04:29:47 PM PDT 24	Aug 14 04:29:49 PM PDT 24	72881854 ps
T3	/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.4217618694	Aug 14 04:30:06 PM PDT 24	Aug 14 04:30:07 PM PDT 24	30144990 ps
T4	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3284240315	Aug 14 04:29:55 PM PDT 24	Aug 14 04:29:57 PM PDT 24	388127143 ps
T10	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.601856027	Aug 14 04:29:52 PM PDT 24	Aug 14 04:29:53 PM PDT 24	61531871 ps
T8	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3730400019	Aug 14 04:29:49 PM PDT 24	Aug 14 04:30:17 PM PDT 24	2716739948 ps
T7	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.277592045	Aug 14 04:29:18 PM PDT 24	Aug 14 04:29:19 PM PDT 24	17812648 ps
T18	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1141896855	Aug 14 04:29:54 PM PDT 24	Aug 14 04:29:56 PM PDT 24	720793657 ps
T6	/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.297441383	Aug 14 04:30:05 PM PDT 24	Aug 14 04:30:08 PM PDT 24	383341955 ps
T29	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.907666648	Aug 14 04:29:50 PM PDT 24	Aug 14 04:30:02 PM PDT 24	1876061544 ps
T5	/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2597218761	Aug 14 04:30:01 PM PDT 24	Aug 14 04:30:03 PM PDT 24	35713550 ps
T11	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3464551047	Aug 14 04:29:56 PM PDT 24	Aug 14 04:30:00 PM PDT 24	208300997 ps
T20	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.206007399	Aug 14 04:29:58 PM PDT 24	Aug 14 04:30:03 PM PDT 24	222540955 ps
T27	/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.786317630	Aug 14 04:30:02 PM PDT 24	Aug 14 04:30:04 PM PDT 24	47148912 ps
T9	/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2693064096	Aug 14 04:29:25 PM PDT 24	Aug 14 04:29:29 PM PDT 24	92608830 ps
T41	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1328401409	Aug 14 04:29:49 PM PDT 24	Aug 14 04:29:50 PM PDT 24	39911935 ps
T67	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.648964587	Aug 14 04:29:50 PM PDT 24	Aug 14 04:29:53 PM PDT 24	192148885 ps
T28	/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.919763778	Aug 14 04:29:41 PM PDT 24	Aug 14 04:29:44 PM PDT 24	46631486 ps
T30	/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.57598954	Aug 14 04:30:11 PM PDT 24	Aug 14 04:30:14 PM PDT 24	1075354922 ps
T33	/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3173034764	Aug 14 04:29:40 PM PDT 24	Aug 14 04:29:46 PM PDT 24	18844003 ps
T34	/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.265504933	Aug 14 04:29:49 PM PDT 24	Aug 14 04:29:51 PM PDT 24	226543910 ps
T12	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.868116959	Aug 14 04:29:42 PM PDT 24	Aug 14 04:29:46 PM PDT 24	91191122 ps
T48	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4086967296	Aug 14 04:29:46 PM PDT 24	Aug 14 04:30:17 PM PDT 24	1374219241 ps
T35	/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2660528977	Aug 14 04:29:53 PM PDT 24	Aug 14 04:29:54 PM PDT 24	69858389 ps
T21	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3910665161	Aug 14 04:29:30 PM PDT 24	Aug 14 04:29:31 PM PDT 24	36055692 ps
T36	/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2984532138	Aug 14 04:30:07 PM PDT 24	Aug 14 04:30:08 PM PDT 24	43407904 ps
T19	/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1722068379	Aug 14 04:29:50 PM PDT 24	Aug 14 04:29:53 PM PDT 24	121888733 ps
T37	/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3918640215	Aug 14 04:29:56 PM PDT 24	Aug 14 04:29:58 PM PDT 24	26326658 ps
T38	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2919666505	Aug 14 04:29:33 PM PDT 24	Aug 14 04:29:34 PM PDT 24	68254999 ps
T16	/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.399153321	Aug 14 04:30:20 PM PDT 24	Aug 14 04:30:22 PM PDT 24	46467002 ps
T71	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2784146174	Aug 14 04:29:27 PM PDT 24	Aug 14 04:29:28 PM PDT 24	87741505 ps
T53	/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3298626255	Aug 14 04:30:04 PM PDT 24	Aug 14 04:30:05 PM PDT 24	37526891 ps
T31	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.514500679	Aug 14 04:29:30 PM PDT 24	Aug 14 04:29:32 PM PDT 24	22729918 ps
T17	/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.594560700	Aug 14 04:29:57 PM PDT 24	Aug 14 04:30:00 PM PDT 24	203539777 ps
T13	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.679956416	Aug 14 04:29:50 PM PDT 24	Aug 14 04:29:52 PM PDT 24	68545675 ps
T32	/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.917154562	Aug 14 04:29:43 PM PDT 24	Aug 14 04:29:45 PM PDT 24	98144888 ps
T68	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3947385317	Aug 14 04:29:47 PM PDT 24	Aug 14 04:29:49 PM PDT 24	90131618 ps
T39	/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2251632789	Aug 14 04:29:51 PM PDT 24	Aug 14 04:29:52 PM PDT 24	45076259 ps
T70	/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3817755791	Aug 14 04:30:08 PM PDT 24	Aug 14 04:30:10 PM PDT 24	104856659 ps
T40	/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3489459151	Aug 14 04:29:25 PM PDT 24	Aug 14 04:29:26 PM PDT 24	235043298 ps
T23	/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1074183057	Aug 14 04:29:57 PM PDT 24	Aug 14 04:29:59 PM PDT 24	235134955 ps
T72	/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3279154546	Aug 14 04:29:55 PM PDT 24	Aug 14 04:29:56 PM PDT 24	26422332 ps
T73	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3836857176	Aug 14 04:29:39 PM PDT 24	Aug 14 04:29:40 PM PDT 24	74040044 ps
T25	/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.377476276	Aug 14 04:30:01 PM PDT 24	Aug 14 04:30:03 PM PDT 24	39148406 ps
T24	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1123072977	Aug 14 04:29:41 PM PDT 24	Aug 14 04:29:43 PM PDT 24	25392864 ps
T42	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1040643741	Aug 14 04:29:58 PM PDT 24	Aug 14 04:29:59 PM PDT 24	17575073 ps
T43	/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1770208276	Aug 14 04:30:03 PM PDT 24	Aug 14 04:30:04 PM PDT 24	32861710 ps
T69	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2561042786	Aug 14 04:29:52 PM PDT 24	Aug 14 04:29:53 PM PDT 24	34937702 ps
T74	/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2811074085	Aug 14 04:30:08 PM PDT 24	Aug 14 04:30:10 PM PDT 24	22630987 ps
T75	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1288415862	Aug 14 04:29:42 PM PDT 24	Aug 14 04:29:43 PM PDT 24	172324804 ps
T44	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2370719460	Aug 14 04:29:56 PM PDT 24	Aug 14 04:29:57 PM PDT 24	29987794 ps
T14	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3643145982	Aug 14 04:29:54 PM PDT 24	Aug 14 04:29:58 PM PDT 24	2527507282 ps
T26	/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3143811145	Aug 14 04:30:08 PM PDT 24	Aug 14 04:30:11 PM PDT 24	389414530 ps
T54	/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2964546656	Aug 14 04:29:50 PM PDT 24	Aug 14 04:29:51 PM PDT 24	25433997 ps
T76	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.795857262	Aug 14 04:29:23 PM PDT 24	Aug 14 04:29:25 PM PDT 24	236278490 ps
T77	/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.320938591	Aug 14 04:29:51 PM PDT 24	Aug 14 04:29:53 PM PDT 24	46816420 ps
T63	/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.995106528	Aug 14 04:29:58 PM PDT 24	Aug 14 04:30:01 PM PDT 24	137431625 ps
T58	/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2757832869	Aug 14 04:30:12 PM PDT 24	Aug 14 04:30:13 PM PDT 24	93518664 ps
T15	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1959877781	Aug 14 04:29:55 PM PDT 24	Aug 14 04:29:58 PM PDT 24	406226857 ps
T60	/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3827737181	Aug 14 04:30:04 PM PDT 24	Aug 14 04:30:06 PM PDT 24	125318366 ps
T78	/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3907881634	Aug 14 04:29:59 PM PDT 24	Aug 14 04:30:07 PM PDT 24	863121016 ps
T59	/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3744796575	Aug 14 04:29:56 PM PDT 24	Aug 14 04:30:01 PM PDT 24	288227298 ps
T79	/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3394964604	Aug 14 04:29:59 PM PDT 24	Aug 14 04:30:02 PM PDT 24	76523784 ps
T80	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2090571709	Aug 14 04:29:25 PM PDT 24	Aug 14 04:29:27 PM PDT 24	1523416410 ps
T81	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2443614734	Aug 14 04:29:37 PM PDT 24	Aug 14 04:29:40 PM PDT 24	93703546 ps
T82	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3947580125	Aug 14 04:30:02 PM PDT 24	Aug 14 04:30:17 PM PDT 24	2900647518 ps
T83	/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.174239613	Aug 14 04:29:40 PM PDT 24	Aug 14 04:29:42 PM PDT 24	311077790 ps
T84	/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3080641571	Aug 14 04:29:59 PM PDT 24	Aug 14 04:30:01 PM PDT 24	32051373 ps
T85	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1399079663	Aug 14 04:29:41 PM PDT 24	Aug 14 04:29:47 PM PDT 24	1185253513 ps
T86	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3839886826	Aug 14 04:29:40 PM PDT 24	Aug 14 04:29:41 PM PDT 24	32898275 ps
T87	/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1988053899	Aug 14 04:29:47 PM PDT 24	Aug 14 04:29:49 PM PDT 24	21264354 ps
T88	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1689125332	Aug 14 04:29:32 PM PDT 24	Aug 14 04:29:35 PM PDT 24	89683976 ps
T64	/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4201655908	Aug 14 04:29:39 PM PDT 24	Aug 14 04:29:42 PM PDT 24	69692089 ps
T89	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.273542507	Aug 14 04:29:27 PM PDT 24	Aug 14 04:29:28 PM PDT 24	33308041 ps
T90	/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2583829428	Aug 14 04:29:53 PM PDT 24	Aug 14 04:29:55 PM PDT 24	34813277 ps
T91	/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.471363698	Aug 14 04:30:03 PM PDT 24	Aug 14 04:30:08 PM PDT 24	1140661094 ps
T92	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2298057982	Aug 14 04:29:43 PM PDT 24	Aug 14 04:29:44 PM PDT 24	13560768 ps
T93	/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1950151587	Aug 14 04:30:14 PM PDT 24	Aug 14 04:30:15 PM PDT 24	22986413 ps
T94	/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3630897474	Aug 14 04:29:42 PM PDT 24	Aug 14 04:29:43 PM PDT 24	96546751 ps
T95	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4273779329	Aug 14 04:29:42 PM PDT 24	Aug 14 04:29:49 PM PDT 24	636407475 ps
T96	/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.200952504	Aug 14 04:30:06 PM PDT 24	Aug 14 04:30:08 PM PDT 24	106146397 ps
T45	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1250760983	Aug 14 04:29:42 PM PDT 24	Aug 14 04:29:43 PM PDT 24	31761358 ps
T97	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2072179927	Aug 14 04:29:45 PM PDT 24	Aug 14 04:29:50 PM PDT 24	375247238 ps
T98	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2489121910	Aug 14 04:29:27 PM PDT 24	Aug 14 04:29:33 PM PDT 24	214824935 ps
T56	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2991433819	Aug 14 04:29:35 PM PDT 24	Aug 14 04:29:37 PM PDT 24	611191890 ps
T99	/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2310534129	Aug 14 04:29:53 PM PDT 24	Aug 14 04:29:54 PM PDT 24	11459536 ps
T46	/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.453731786	Aug 14 04:30:02 PM PDT 24	Aug 14 04:30:03 PM PDT 24	18290155 ps
T100	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.4111421463	Aug 14 04:29:53 PM PDT 24	Aug 14 04:29:59 PM PDT 24	582477177 ps
T101	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1352188665	Aug 14 04:29:49 PM PDT 24	Aug 14 04:29:52 PM PDT 24	82687398 ps
T102	/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.947822338	Aug 14 04:29:51 PM PDT 24	Aug 14 04:29:53 PM PDT 24	25876283 ps
T65	/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2402539381	Aug 14 04:29:48 PM PDT 24	Aug 14 04:29:51 PM PDT 24	439938164 ps
T103	/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1124257588	Aug 14 04:29:41 PM PDT 24	Aug 14 04:29:44 PM PDT 24	426136368 ps
T104	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1888248237	Aug 14 04:29:38 PM PDT 24	Aug 14 04:29:40 PM PDT 24	142835553 ps
T105	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1581225237	Aug 14 04:30:08 PM PDT 24	Aug 14 04:30:10 PM PDT 24	22281106 ps
T49	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2496504764	Aug 14 04:29:55 PM PDT 24	Aug 14 04:29:56 PM PDT 24	17223758 ps
T106	/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.251946233	Aug 14 04:30:05 PM PDT 24	Aug 14 04:30:09 PM PDT 24	96648668 ps
T66	/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.107049218	Aug 14 04:29:42 PM PDT 24	Aug 14 04:29:46 PM PDT 24	115759054 ps
T107	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.575811830	Aug 14 04:29:33 PM PDT 24	Aug 14 04:29:35 PM PDT 24	70493072 ps
T108	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2796111010	Aug 14 04:29:24 PM PDT 24	Aug 14 04:29:25 PM PDT 24	202530053 ps
T50	/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3276155841	Aug 14 04:29:53 PM PDT 24	Aug 14 04:29:54 PM PDT 24	32667158 ps
T109	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2900225911	Aug 14 04:30:03 PM PDT 24	Aug 14 04:30:05 PM PDT 24	68230843 ps
T110	/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1961086982	Aug 14 04:30:03 PM PDT 24	Aug 14 04:30:05 PM PDT 24	30873397 ps
T111	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1457638299	Aug 14 04:29:57 PM PDT 24	Aug 14 04:29:59 PM PDT 24	35779751 ps
T47	/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3751803753	Aug 14 04:29:57 PM PDT 24	Aug 14 04:29:58 PM PDT 24	12496553 ps
T112	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2921390302	Aug 14 04:29:37 PM PDT 24	Aug 14 04:29:38 PM PDT 24	45183570 ps
T113	/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1372469482	Aug 14 04:30:08 PM PDT 24	Aug 14 04:30:09 PM PDT 24	46831207 ps
T61	/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2647633189	Aug 14 04:29:41 PM PDT 24	Aug 14 04:29:43 PM PDT 24	197776434 ps
T114	/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2708935851	Aug 14 04:30:06 PM PDT 24	Aug 14 04:30:07 PM PDT 24	53248124 ps
T115	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3665724911	Aug 14 04:29:51 PM PDT 24	Aug 14 04:29:54 PM PDT 24	232112455 ps
T116	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.980624642	Aug 14 04:29:32 PM PDT 24	Aug 14 04:29:34 PM PDT 24	421697887 ps
T117	/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2759435235	Aug 14 04:29:55 PM PDT 24	Aug 14 04:29:57 PM PDT 24	40092594 ps
T118	/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2506379068	Aug 14 04:29:47 PM PDT 24	Aug 14 04:29:49 PM PDT 24	45490279 ps
T119	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.653021698	Aug 14 04:29:28 PM PDT 24	Aug 14 04:29:30 PM PDT 24	50143680 ps
T120	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3602749617	Aug 14 04:30:04 PM PDT 24	Aug 14 04:30:06 PM PDT 24	452725984 ps
T121	/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.879103475	Aug 14 04:29:40 PM PDT 24	Aug 14 04:29:43 PM PDT 24	182872710 ps
T122	/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2679422816	Aug 14 04:29:59 PM PDT 24	Aug 14 04:30:05 PM PDT 24	16831578 ps
T123	/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1641494972	Aug 14 04:29:59 PM PDT 24	Aug 14 04:30:01 PM PDT 24	25928622 ps
T124	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1268970450	Aug 14 04:29:42 PM PDT 24	Aug 14 04:29:44 PM PDT 24	303424943 ps
T22	/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1873679101	Aug 14 04:29:51 PM PDT 24	Aug 14 04:29:53 PM PDT 24	55661147 ps
T125	/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3102819030	Aug 14 04:29:42 PM PDT 24	Aug 14 04:29:43 PM PDT 24	71977069 ps
T126	/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1265286886	Aug 14 04:29:53 PM PDT 24	Aug 14 04:29:57 PM PDT 24	128319427 ps
T127	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3610425519	Aug 14 04:29:57 PM PDT 24	Aug 14 04:29:58 PM PDT 24	21456442 ps
T128	/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1897821478	Aug 14 04:29:58 PM PDT 24	Aug 14 04:30:01 PM PDT 24	461214412 ps
T129	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2472969688	Aug 14 04:29:38 PM PDT 24	Aug 14 04:29:39 PM PDT 24	36578938 ps
T130	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2939063592	Aug 14 04:29:40 PM PDT 24	Aug 14 04:29:40 PM PDT 24	11899723 ps
T131	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2230037862	Aug 14 04:29:42 PM PDT 24	Aug 14 04:29:45 PM PDT 24	351932553 ps
T132	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1883454153	Aug 14 04:29:58 PM PDT 24	Aug 14 04:29:59 PM PDT 24	200295703 ps
T133	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3247051161	Aug 14 04:29:39 PM PDT 24	Aug 14 04:29:47 PM PDT 24	632628867 ps
T134	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.113673798	Aug 14 04:29:42 PM PDT 24	Aug 14 04:29:43 PM PDT 24	31777762 ps
T135	/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3065303307	Aug 14 04:30:01 PM PDT 24	Aug 14 04:30:02 PM PDT 24	21387088 ps
T136	/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1758538671	Aug 14 04:29:25 PM PDT 24	Aug 14 04:29:28 PM PDT 24	135638077 ps
T62	/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.118231290	Aug 14 04:29:53 PM PDT 24	Aug 14 04:29:56 PM PDT 24	49769703 ps
T137	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2702105396	Aug 14 04:29:45 PM PDT 24	Aug 14 04:29:47 PM PDT 24	60386802 ps
T138	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1266052731	Aug 14 04:29:40 PM PDT 24	Aug 14 04:30:20 PM PDT 24	7277682501 ps
T139	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2793943724	Aug 14 04:29:39 PM PDT 24	Aug 14 04:29:41 PM PDT 24	125761887 ps
T140	/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3489570284	Aug 14 04:29:32 PM PDT 24	Aug 14 04:29:33 PM PDT 24	32729162 ps
T141	/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1330268230	Aug 14 04:29:51 PM PDT 24	Aug 14 04:29:52 PM PDT 24	24836792 ps
T142	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3330727611	Aug 14 04:29:44 PM PDT 24	Aug 14 04:29:45 PM PDT 24	37483242 ps
T143	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2545171864	Aug 14 04:29:28 PM PDT 24	Aug 14 04:29:42 PM PDT 24	619713889 ps
T144	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.693332089	Aug 14 04:29:42 PM PDT 24	Aug 14 04:29:48 PM PDT 24	2512839576 ps
T145	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1825750268	Aug 14 04:30:07 PM PDT 24	Aug 14 04:30:18 PM PDT 24	89859616 ps
T146	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2408261858	Aug 14 04:29:30 PM PDT 24	Aug 14 04:29:31 PM PDT 24	126201159 ps
T147	/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2697096990	Aug 14 04:29:47 PM PDT 24	Aug 14 04:29:48 PM PDT 24	42735846 ps
T148	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1880600501	Aug 14 04:29:24 PM PDT 24	Aug 14 04:29:29 PM PDT 24	734806856 ps
T149	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.615653078	Aug 14 04:29:50 PM PDT 24	Aug 14 04:29:57 PM PDT 24	134559082 ps
T150	/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2061623133	Aug 14 04:30:10 PM PDT 24	Aug 14 04:30:12 PM PDT 24	35164304 ps
T151	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2119359262	Aug 14 04:29:47 PM PDT 24	Aug 14 04:29:55 PM PDT 24	5118715299 ps
T152	/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4128628810	Aug 14 04:29:52 PM PDT 24	Aug 14 04:29:53 PM PDT 24	29878998 ps
T153	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3627409355	Aug 14 04:29:54 PM PDT 24	Aug 14 04:30:13 PM PDT 24	4131267536 ps
T51	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.160967517	Aug 14 04:29:47 PM PDT 24	Aug 14 04:29:48 PM PDT 24	14350680 ps
T154	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3325510103	Aug 14 04:29:51 PM PDT 24	Aug 14 04:29:53 PM PDT 24	47202609 ps
T155	/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.984855496	Aug 14 04:30:08 PM PDT 24	Aug 14 04:30:10 PM PDT 24	40597167 ps
T156	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.180511127	Aug 14 04:30:01 PM PDT 24	Aug 14 04:30:04 PM PDT 24	41063460 ps
T57	/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2678044061	Aug 14 04:29:53 PM PDT 24	Aug 14 04:29:57 PM PDT 24	317372442 ps
T157	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2842618873	Aug 14 04:29:57 PM PDT 24	Aug 14 04:29:58 PM PDT 24	51485664 ps
T158	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.141806839	Aug 14 04:29:37 PM PDT 24	Aug 14 04:29:39 PM PDT 24	91726571 ps
T159	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2530329121	Aug 14 04:29:45 PM PDT 24	Aug 14 04:29:54 PM PDT 24	2043254812 ps
T160	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.142525595	Aug 14 04:29:52 PM PDT 24	Aug 14 04:29:54 PM PDT 24	80424962 ps
T161	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3645172213	Aug 14 04:29:31 PM PDT 24	Aug 14 04:29:33 PM PDT 24	199567234 ps
T162	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2276876275	Aug 14 04:29:25 PM PDT 24	Aug 14 04:29:35 PM PDT 24	3588051578 ps
T163	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2199730907	Aug 14 04:29:38 PM PDT 24	Aug 14 04:29:40 PM PDT 24	81508290 ps
T164	/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3851826734	Aug 14 04:30:07 PM PDT 24	Aug 14 04:30:08 PM PDT 24	53822243 ps
T165	/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.497496525	Aug 14 04:29:55 PM PDT 24	Aug 14 04:29:57 PM PDT 24	29846605 ps
T166	/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3058380003	Aug 14 04:29:47 PM PDT 24	Aug 14 04:29:48 PM PDT 24	40094869 ps
T167	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3203970659	Aug 14 04:29:51 PM PDT 24	Aug 14 04:29:52 PM PDT 24	97662483 ps
T168	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1694624100	Aug 14 04:29:46 PM PDT 24	Aug 14 04:29:49 PM PDT 24	46948305 ps
T169	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.4223370463	Aug 14 04:29:29 PM PDT 24	Aug 14 04:29:30 PM PDT 24	52071278 ps
T170	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.4288636692	Aug 14 04:29:28 PM PDT 24	Aug 14 04:29:35 PM PDT 24	512507380 ps
T171	/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2989147228	Aug 14 04:29:58 PM PDT 24	Aug 14 04:29:59 PM PDT 24	22616219 ps
T172	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.631748116	Aug 14 04:29:30 PM PDT 24	Aug 14 04:29:31 PM PDT 24	192185597 ps
T173	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3486103326	Aug 14 04:29:25 PM PDT 24	Aug 14 04:29:27 PM PDT 24	329579969 ps
T174	/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2030560589	Aug 14 04:29:57 PM PDT 24	Aug 14 04:29:58 PM PDT 24	15816714 ps
T175	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.593835299	Aug 14 04:29:32 PM PDT 24	Aug 14 04:29:34 PM PDT 24	230236010 ps
T52	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1935880705	Aug 14 04:29:24 PM PDT 24	Aug 14 04:29:25 PM PDT 24	60528997 ps
T176	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1932051545	Aug 14 04:29:49 PM PDT 24	Aug 14 04:29:51 PM PDT 24	54194516 ps
T177	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2767547326	Aug 14 04:29:55 PM PDT 24	Aug 14 04:29:58 PM PDT 24	444914726 ps
T178	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1257875590	Aug 14 04:29:48 PM PDT 24	Aug 14 04:29:51 PM PDT 24	257177076 ps
T179	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2273200428	Aug 14 04:29:33 PM PDT 24	Aug 14 04:29:34 PM PDT 24	22282098 ps
T180	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.762788891	Aug 14 04:29:49 PM PDT 24	Aug 14 04:29:50 PM PDT 24	16974636 ps
T181	/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.824723021	Aug 14 04:29:42 PM PDT 24	Aug 14 04:29:46 PM PDT 24	27459540 ps
T55	/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.406075271	Aug 14 04:29:51 PM PDT 24	Aug 14 04:29:53 PM PDT 24	265270614 ps
T182	/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3704166681	Aug 14 04:29:50 PM PDT 24	Aug 14 04:29:53 PM PDT 24	229456807 ps
T183	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3513258262	Aug 14 04:29:57 PM PDT 24	Aug 14 04:29:58 PM PDT 24	617033632 ps
T184	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3998692910	Aug 14 04:29:32 PM PDT 24	Aug 14 04:29:35 PM PDT 24	148289379 ps
T185	/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1348886736	Aug 14 04:29:52 PM PDT 24	Aug 14 04:29:53 PM PDT 24	23112917 ps

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3284240315
Short name	T4
Test name
Test status
Simulation time	388127143 ps
CPU time	1.72 seconds
Started	Aug 14 04:29:55 PM PDT 24
Finished	Aug 14 04:29:57 PM PDT 24
Peak memory	219920 kb
Host	smart-3332265c-136d-43e7-b07c-3fb6e8d7a179
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328424 0315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3284240315
Directory	/workspace/7.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_intg_err.2693064096
Short name	T9
Test name
Test status
Simulation time	92608830 ps
CPU time	3.44 seconds
Started	Aug 14 04:29:25 PM PDT 24
Finished	Aug 14 04:29:29 PM PDT 24
Peak memory	218352 kb
Host	smart-1ba56dfd-52e5-42e1-8534-8dcc729ab962
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693064096 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_intg_ err.2693064096
Directory	/workspace/1.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_intg_err.1959877781
Short name	T15
Test name
Test status
Simulation time	406226857 ps
CPU time	2.91 seconds
Started	Aug 14 04:29:55 PM PDT 24
Finished	Aug 14 04:29:58 PM PDT 24
Peak memory	223140 kb
Host	smart-a29bb5cc-3797-49a8-a805-4d188bf8790a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959877781 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_intg _err.1959877781
Directory	/workspace/18.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_hw_reset.3910665161
Short name	T21
Test name
Test status
Simulation time	36055692 ps
CPU time	1.13 seconds
Started	Aug 14 04:29:30 PM PDT 24
Finished	Aug 14 04:29:31 PM PDT 24
Peak memory	218656 kb
Host	smart-352eb3ad-435e-4217-9356-6a313f49bc28
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910665161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_hw_rese t.3910665161
Directory	/workspace/0.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_errors.297441383
Short name	T6
Test name
Test status
Simulation time	383341955 ps
CPU time	2.72 seconds
Started	Aug 14 04:30:05 PM PDT 24
Finished	Aug 14 04:30:08 PM PDT 24
Peak memory	218208 kb
Host	smart-5956e646-3f34-46e3-b2f1-31666d36714a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297441383 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_errors.297441383
Directory	/workspace/19.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_same_csr_outstanding.280798447
Short name	T1
Test name
Test status
Simulation time	21415402 ps
CPU time	1.54 seconds
Started	Aug 14 04:29:50 PM PDT 24
Finished	Aug 14 04:29:52 PM PDT 24
Peak memory	212144 kb
Host	smart-d4897e25-069d-4928-b20e-a5a38e4eef27
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280798447 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl _same_csr_outstanding.280798447
Directory	/workspace/15.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_intg_err.1722068379
Short name	T19
Test name
Test status
Simulation time	121888733 ps
CPU time	2.87 seconds
Started	Aug 14 04:29:50 PM PDT 24
Finished	Aug 14 04:29:53 PM PDT 24
Peak memory	223112 kb
Host	smart-db047bda-4536-4480-a97e-4d0f3e6e1423
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722068379 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_intg _err.1722068379
Directory	/workspace/15.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_errors.919763778
Short name	T28
Test name
Test status
Simulation time	46631486 ps
CPU time	3.18 seconds
Started	Aug 14 04:29:41 PM PDT 24
Finished	Aug 14 04:29:44 PM PDT 24
Peak memory	218180 kb
Host	smart-ef1ceaa4-dd7d-416a-b0af-56d42182b04e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919763778 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_errors.919763778
Directory	/workspace/13.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_intg_err.995106528
Short name	T63
Test name
Test status
Simulation time	137431625 ps
CPU time	3.6 seconds
Started	Aug 14 04:29:58 PM PDT 24
Finished	Aug 14 04:30:01 PM PDT 24
Peak memory	223232 kb
Host	smart-0b08f978-bf58-4729-8d4f-0aa396b8b1e4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995106528 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_intg_e rr.995106528
Directory	/workspace/4.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_aliasing.206007399
Short name	T20
Test name
Test status
Simulation time	222540955 ps
CPU time	5.73 seconds
Started	Aug 14 04:29:58 PM PDT 24
Finished	Aug 14 04:30:03 PM PDT 24
Peak memory	209416 kb
Host	smart-983859bf-48ad-46ad-9907-fbbad4cff105
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206007399 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 6.lc_ctrl_jtag_csr_aliasing.206007399
Directory	/workspace/6.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_intg_err.2678044061
Short name	T57
Test name
Test status
Simulation time	317372442 ps
CPU time	3.34 seconds
Started	Aug 14 04:29:53 PM PDT 24
Finished	Aug 14 04:29:57 PM PDT 24
Peak memory	218224 kb
Host	smart-521987f7-5e7a-49e7-ac96-ea4140ac9b5d
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678044061 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_intg_ err.2678044061
Directory	/workspace/0.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_same_csr_outstanding.3817755791
Short name	T70
Test name
Test status
Simulation time	104856659 ps
CPU time	1.85 seconds
Started	Aug 14 04:30:08 PM PDT 24
Finished	Aug 14 04:30:10 PM PDT 24
Peak memory	210000 kb
Host	smart-4fa9f2e9-ecee-4966-a9a5-a3ea8f80b741
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817755791 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl _same_csr_outstanding.3817755791
Directory	/workspace/6.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_intg_err.2402539381
Short name	T65
Test name
Test status
Simulation time	439938164 ps
CPU time	2.96 seconds
Started	Aug 14 04:29:48 PM PDT 24
Finished	Aug 14 04:29:51 PM PDT 24
Peak memory	223280 kb
Host	smart-c0bcd361-20e5-4aad-982a-327485b4b2f8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402539381 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_intg _err.2402539381
Directory	/workspace/10.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_intg_err.107049218
Short name	T66
Test name
Test status
Simulation time	115759054 ps
CPU time	4.01 seconds
Started	Aug 14 04:29:42 PM PDT 24
Finished	Aug 14 04:29:46 PM PDT 24
Peak memory	218260 kb
Host	smart-21f6a2c2-a5e7-40cf-b297-e42c84315218
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=107049218 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_intg_ err.107049218
Directory	/workspace/17.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_intg_err.2647633189
Short name	T61
Test name
Test status
Simulation time	197776434 ps
CPU time	2.07 seconds
Started	Aug 14 04:29:41 PM PDT 24
Finished	Aug 14 04:29:43 PM PDT 24
Peak memory	218332 kb
Host	smart-c9262971-b9ba-4c5d-acb7-ddb91f53a904
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647633189 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_intg_ err.2647633189
Directory	/workspace/2.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_intg_err.406075271
Short name	T55
Test name
Test status
Simulation time	265270614 ps
CPU time	2.06 seconds
Started	Aug 14 04:29:51 PM PDT 24
Finished	Aug 14 04:29:53 PM PDT 24
Peak memory	222752 kb
Host	smart-733c7ed8-ae57-4de2-98ef-70d157c98574
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406075271 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_intg_ err.406075271
Directory	/workspace/16.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_intg_err.4201655908
Short name	T64
Test name
Test status
Simulation time	69692089 ps
CPU time	3.04 seconds
Started	Aug 14 04:29:39 PM PDT 24
Finished	Aug 14 04:29:42 PM PDT 24
Peak memory	222736 kb
Host	smart-a53a72b2-a7d1-4d07-a2de-ba353c41bc36
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201655908 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_intg_ err.4201655908
Directory	/workspace/3.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_intg_err.2991433819
Short name	T56
Test name
Test status
Simulation time	611191890 ps
CPU time	1.78 seconds
Started	Aug 14 04:29:35 PM PDT 24
Finished	Aug 14 04:29:37 PM PDT 24
Peak memory	222780 kb
Host	smart-2b13e781-9d7b-4fe4-a961-56a203938666
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991433819 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_intg_ err.2991433819
Directory	/workspace/6.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_intg_err.118231290
Short name	T62
Test name
Test status
Simulation time	49769703 ps
CPU time	2.35 seconds
Started	Aug 14 04:29:53 PM PDT 24
Finished	Aug 14 04:29:56 PM PDT 24
Peak memory	218208 kb
Host	smart-7c4cdeb9-d342-4649-bab5-cdea577a9063
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118231290 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_intg_e rr.118231290
Directory	/workspace/7.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_mem_rw_with_rand_reset.2597218761
Short name	T5
Test name
Test status
Simulation time	35713550 ps
CPU time	1.47 seconds
Started	Aug 14 04:30:01 PM PDT 24
Finished	Aug 14 04:30:03 PM PDT 24
Peak memory	218500 kb
Host	smart-b2e60ffe-9960-42f0-a07c-c448c3665384
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2597218761 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.lc_ctrl_csr_mem_rw_with_rand_reset.2597218761
Directory	/workspace/10.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_aliasing.2273200428
Short name	T179
Test name
Test status
Simulation time	22282098 ps
CPU time	1.12 seconds
Started	Aug 14 04:29:33 PM PDT 24
Finished	Aug 14 04:29:34 PM PDT 24
Peak memory	209056 kb
Host	smart-f6e69bbd-dd6c-4f32-ae78-d4104afb5212
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273200428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_aliasin g.2273200428
Directory	/workspace/0.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_bit_bash.2796111010
Short name	T108
Test name
Test status
Simulation time	202530053 ps
CPU time	1.41 seconds
Started	Aug 14 04:29:24 PM PDT 24
Finished	Aug 14 04:29:25 PM PDT 24
Peak memory	209972 kb
Host	smart-5d469f90-1e62-46a4-b40b-dced64a4c4b0
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796111010 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_bit_bas h.2796111010
Directory	/workspace/0.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_mem_rw_with_rand_reset.1123072977
Short name	T24
Test name
Test status
Simulation time	25392864 ps
CPU time	1.78 seconds
Started	Aug 14 04:29:41 PM PDT 24
Finished	Aug 14 04:29:43 PM PDT 24
Peak memory	218356 kb
Host	smart-6ea72c71-c15e-46d1-be73-3c9806fc561a
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123072977 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.lc_ctrl_csr_mem_rw_with_rand_reset.1123072977
Directory	/workspace/0.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_csr_rw.277592045
Short name	T7
Test name
Test status
Simulation time	17812648 ps
CPU time	0.91 seconds
Started	Aug 14 04:29:18 PM PDT 24
Finished	Aug 14 04:29:19 PM PDT 24
Peak memory	210028 kb
Host	smart-1970d13a-02cf-462f-8f20-2fd2c95a6919
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277592045 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_csr_rw.277592045
Directory	/workspace/0.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_alert_test.2784146174
Short name	T71
Test name
Test status
Simulation time	87741505 ps
CPU time	1.82 seconds
Started	Aug 14 04:29:27 PM PDT 24
Finished	Aug 14 04:29:28 PM PDT 24
Peak memory	210008 kb
Host	smart-69f9e765-e6b1-4165-b6dd-ac1fcc29ac35
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784146174 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 0.lc_ctrl_jtag_alert_test.2784146174
Directory	/workspace/0.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_aliasing.4288636692
Short name	T170
Test name
Test status
Simulation time	512507380 ps
CPU time	6.87 seconds
Started	Aug 14 04:29:28 PM PDT 24
Finished	Aug 14 04:29:35 PM PDT 24
Peak memory	209328 kb
Host	smart-63d770dd-0147-48c8-a8f2-28b59f2c2187
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288636692 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_aliasing.4288636692
Directory	/workspace/0.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_bit_bash.2545171864
Short name	T143
Test name
Test status
Simulation time	619713889 ps
CPU time	14.23 seconds
Started	Aug 14 04:29:28 PM PDT 24
Finished	Aug 14 04:29:42 PM PDT 24
Peak memory	209988 kb
Host	smart-171e5465-047f-4539-875a-39c0e87fdd15
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545171864 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 0.lc_ctrl_jtag_csr_bit_bash.2545171864
Directory	/workspace/0.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_hw_reset.795857262
Short name	T76
Test name
Test status
Simulation time	236278490 ps
CPU time	2.01 seconds
Started	Aug 14 04:29:23 PM PDT 24
Finished	Aug 14 04:29:25 PM PDT 24
Peak memory	211232 kb
Host	smart-75af9c63-c8b9-4aeb-8da6-8149e98278ae
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795857262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 0.lc_ctrl_jtag_csr_hw_reset.795857262
Directory	/workspace/0.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3486103326
Short name	T173
Test name
Test status
Simulation time	329579969 ps
CPU time	1.48 seconds
Started	Aug 14 04:29:25 PM PDT 24
Finished	Aug 14 04:29:27 PM PDT 24
Peak memory	219384 kb
Host	smart-637309d3-f347-4b39-ac16-e9ccb54a9e5e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348610 3326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3486103326
Directory	/workspace/0.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_csr_rw.3513258262
Short name	T183
Test name
Test status
Simulation time	617033632 ps
CPU time	1.39 seconds
Started	Aug 14 04:29:57 PM PDT 24
Finished	Aug 14 04:29:58 PM PDT 24
Peak memory	210036 kb
Host	smart-33ba9d9e-6f47-466c-a9a4-735d5de3821a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513258262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_csr_rw.3513258262
Directory	/workspace/0.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_jtag_same_csr_outstanding.631748116
Short name	T172
Test name
Test status
Simulation time	192185597 ps
CPU time	1.25 seconds
Started	Aug 14 04:29:30 PM PDT 24
Finished	Aug 14 04:29:31 PM PDT 24
Peak memory	212100 kb
Host	smart-3974f02c-c88a-478b-bdb4-eec1e2b2337d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631748116 -assert nopostproc +UVM_TESTNAM E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_jtag_same_csr_outstanding.631748116
Directory	/workspace/0.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_same_csr_outstanding.3102819030
Short name	T125
Test name
Test status
Simulation time	71977069 ps
CPU time	1.19 seconds
Started	Aug 14 04:29:42 PM PDT 24
Finished	Aug 14 04:29:43 PM PDT 24
Peak memory	212000 kb
Host	smart-1fcc4fa6-a715-4592-bfd0-89d4212c3ad1
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102819030 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl _same_csr_outstanding.3102819030
Directory	/workspace/0.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/0.lc_ctrl_tl_errors.3704166681
Short name	T182
Test name
Test status
Simulation time	229456807 ps
CPU time	3.21 seconds
Started	Aug 14 04:29:50 PM PDT 24
Finished	Aug 14 04:29:53 PM PDT 24
Peak memory	218204 kb
Host	smart-e4e48e06-02e0-4dcd-a1bd-d53fd2ab7f93
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3704166681 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.lc_ctrl_tl_errors.3704166681
Directory	/workspace/0.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_aliasing.2919666505
Short name	T38
Test name
Test status
Simulation time	68254999 ps
CPU time	1.07 seconds
Started	Aug 14 04:29:33 PM PDT 24
Finished	Aug 14 04:29:34 PM PDT 24
Peak memory	210008 kb
Host	smart-4d879dcf-f9aa-491e-9f1f-7c00a98979cd
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919666505 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_aliasin g.2919666505
Directory	/workspace/1.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_bit_bash.1935880705
Short name	T52
Test name
Test status
Simulation time	60528997 ps
CPU time	1.15 seconds
Started	Aug 14 04:29:24 PM PDT 24
Finished	Aug 14 04:29:25 PM PDT 24
Peak memory	209324 kb
Host	smart-9c2c309e-5c1d-444a-9ff3-70b1b035129d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935880705 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_bit_bas h.1935880705
Directory	/workspace/1.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_hw_reset.2921390302
Short name	T112
Test name
Test status
Simulation time	45183570 ps
CPU time	0.88 seconds
Started	Aug 14 04:29:37 PM PDT 24
Finished	Aug 14 04:29:38 PM PDT 24
Peak memory	210496 kb
Host	smart-5a6f665c-a0da-4aa9-afeb-9b22dfa40949
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2921390302 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_hw_rese t.2921390302
Directory	/workspace/1.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_mem_rw_with_rand_reset.514500679
Short name	T31
Test name
Test status
Simulation time	22729918 ps
CPU time	1.54 seconds
Started	Aug 14 04:29:30 PM PDT 24
Finished	Aug 14 04:29:32 PM PDT 24
Peak memory	222204 kb
Host	smart-d8a8bbae-8bc4-433b-8068-7fb20496734f
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514500679 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 1.lc_ctrl_csr_mem_rw_with_rand_reset.514500679
Directory	/workspace/1.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_csr_rw.2939063592
Short name	T130
Test name
Test status
Simulation time	11899723 ps
CPU time	0.87 seconds
Started	Aug 14 04:29:40 PM PDT 24
Finished	Aug 14 04:29:40 PM PDT 24
Peak memory	210028 kb
Host	smart-902e555d-8caf-48cd-852c-2583c6a3291b
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939063592 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_csr_rw.2939063592
Directory	/workspace/1.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_alert_test.575811830
Short name	T107
Test name
Test status
Simulation time	70493072 ps
CPU time	1.34 seconds
Started	Aug 14 04:29:33 PM PDT 24
Finished	Aug 14 04:29:35 PM PDT 24
Peak memory	210004 kb
Host	smart-43863a39-d5c9-45e2-8792-04ef1f6b1567
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575811830 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 1.lc_ctrl_jtag_alert_test.575811830
Directory	/workspace/1.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_aliasing.2530329121
Short name	T159
Test name
Test status
Simulation time	2043254812 ps
CPU time	9.1 seconds
Started	Aug 14 04:29:45 PM PDT 24
Finished	Aug 14 04:29:54 PM PDT 24
Peak memory	209832 kb
Host	smart-9135cac2-add7-4063-b305-c91dae79452d
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530329121 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_aliasing.2530329121
Directory	/workspace/1.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_bit_bash.1266052731
Short name	T138
Test name
Test status
Simulation time	7277682501 ps
CPU time	40.07 seconds
Started	Aug 14 04:29:40 PM PDT 24
Finished	Aug 14 04:30:20 PM PDT 24
Peak memory	210060 kb
Host	smart-eac1a7da-981e-4aef-9634-65e48a2dfb75
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266052731 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_bit_bash.1266052731
Directory	/workspace/1.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_hw_reset.2489121910
Short name	T98
Test name
Test status
Simulation time	214824935 ps
CPU time	5.28 seconds
Started	Aug 14 04:29:27 PM PDT 24
Finished	Aug 14 04:29:33 PM PDT 24
Peak memory	211864 kb
Host	smart-100b65fb-f2fd-46b7-8532-b6152fa9dc17
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489121910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 1.lc_ctrl_jtag_csr_hw_reset.2489121910
Directory	/workspace/1.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2767547326
Short name	T177
Test name
Test status
Simulation time	444914726 ps
CPU time	2.45 seconds
Started	Aug 14 04:29:55 PM PDT 24
Finished	Aug 14 04:29:58 PM PDT 24
Peak memory	219756 kb
Host	smart-13c8c883-9bf5-4c5d-940f-258191a5c76d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276754 7326 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2767547326
Directory	/workspace/1.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_csr_rw.1288415862
Short name	T75
Test name
Test status
Simulation time	172324804 ps
CPU time	1.23 seconds
Started	Aug 14 04:29:42 PM PDT 24
Finished	Aug 14 04:29:43 PM PDT 24
Peak memory	210052 kb
Host	smart-020b64b9-2110-40a8-a8b4-9638c662a580
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288415862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_csr_rw.1288415862
Directory	/workspace/1.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_jtag_same_csr_outstanding.2199730907
Short name	T163
Test name
Test status
Simulation time	81508290 ps
CPU time	1.27 seconds
Started	Aug 14 04:29:38 PM PDT 24
Finished	Aug 14 04:29:40 PM PDT 24
Peak memory	210032 kb
Host	smart-79be6017-c569-4652-8f9b-b0124c3f765c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199730907 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_jtag_same_csr_outstanding.2199730907
Directory	/workspace/1.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_same_csr_outstanding.3279154546
Short name	T72
Test name
Test status
Simulation time	26422332 ps
CPU time	1.06 seconds
Started	Aug 14 04:29:55 PM PDT 24
Finished	Aug 14 04:29:56 PM PDT 24
Peak memory	209572 kb
Host	smart-b877307c-c3eb-45d1-a59a-56c385a14037
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279154546 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl _same_csr_outstanding.3279154546
Directory	/workspace/1.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/1.lc_ctrl_tl_errors.1758538671
Short name	T136
Test name
Test status
Simulation time	135638077 ps
CPU time	3.44 seconds
Started	Aug 14 04:29:25 PM PDT 24
Finished	Aug 14 04:29:28 PM PDT 24
Peak memory	218632 kb
Host	smart-d6c56b7a-904f-4df4-aaf4-21402f62cc31
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758538671 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.lc_ctrl_tl_errors.1758538671
Directory	/workspace/1.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_csr_rw.2030560589
Short name	T174
Test name
Test status
Simulation time	15816714 ps
CPU time	0.86 seconds
Started	Aug 14 04:29:57 PM PDT 24
Finished	Aug 14 04:29:58 PM PDT 24
Peak memory	209836 kb
Host	smart-7d4d3a5e-107f-4398-a82b-4e00de2a8d06
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030560589 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_csr_rw.2030560589
Directory	/workspace/10.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_same_csr_outstanding.4217618694
Short name	T3
Test name
Test status
Simulation time	30144990 ps
CPU time	1.34 seconds
Started	Aug 14 04:30:06 PM PDT 24
Finished	Aug 14 04:30:07 PM PDT 24
Peak memory	210040 kb
Host	smart-3122d290-874d-4d2d-9c8b-fcada07c26f0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217618694 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctr l_same_csr_outstanding.4217618694
Directory	/workspace/10.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/10.lc_ctrl_tl_errors.174239613
Short name	T83
Test name
Test status
Simulation time	311077790 ps
CPU time	2.09 seconds
Started	Aug 14 04:29:40 PM PDT 24
Finished	Aug 14 04:29:42 PM PDT 24
Peak memory	218208 kb
Host	smart-c6bf6898-d442-4ccc-82b1-bf9517075432
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174239613 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.lc_ctrl_tl_errors.174239613
Directory	/workspace/10.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_mem_rw_with_rand_reset.4128628810
Short name	T152
Test name
Test status
Simulation time	29878998 ps
CPU time	1.14 seconds
Started	Aug 14 04:29:52 PM PDT 24
Finished	Aug 14 04:29:53 PM PDT 24
Peak memory	218296 kb
Host	smart-87b04a4c-31b4-4b67-8dfe-dfa77968d140
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128628810 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.lc_ctrl_csr_mem_rw_with_rand_reset.4128628810
Directory	/workspace/11.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_csr_rw.3851826734
Short name	T164
Test name
Test status
Simulation time	53822243 ps
CPU time	1.04 seconds
Started	Aug 14 04:30:07 PM PDT 24
Finished	Aug 14 04:30:08 PM PDT 24
Peak memory	209808 kb
Host	smart-2eda6cff-f32e-4c33-9458-4d6b63c2252a
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851826734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_csr_rw.3851826734
Directory	/workspace/11.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_same_csr_outstanding.2984532138
Short name	T36
Test name
Test status
Simulation time	43407904 ps
CPU time	0.95 seconds
Started	Aug 14 04:30:07 PM PDT 24
Finished	Aug 14 04:30:08 PM PDT 24
Peak memory	209976 kb
Host	smart-cc5bf1ae-93b2-43d9-9839-fdefa114d94c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984532138 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctr l_same_csr_outstanding.2984532138
Directory	/workspace/11.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_errors.984855496
Short name	T155
Test name
Test status
Simulation time	40597167 ps
CPU time	2.67 seconds
Started	Aug 14 04:30:08 PM PDT 24
Finished	Aug 14 04:30:10 PM PDT 24
Peak memory	218204 kb
Host	smart-3cc116f4-5a16-4acf-948d-e1efbcc6bb59
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984855496 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_errors.984855496
Directory	/workspace/11.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/11.lc_ctrl_tl_intg_err.1074183057
Short name	T23
Test name
Test status
Simulation time	235134955 ps
CPU time	2.46 seconds
Started	Aug 14 04:29:57 PM PDT 24
Finished	Aug 14 04:29:59 PM PDT 24
Peak memory	218196 kb
Host	smart-5b0f947a-1f5e-45c6-8d75-67c26d2229a4
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074183057 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.lc_ctrl_tl_intg _err.1074183057
Directory	/workspace/11.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_mem_rw_with_rand_reset.2757832869
Short name	T58
Test name
Test status
Simulation time	93518664 ps
CPU time	1.47 seconds
Started	Aug 14 04:30:12 PM PDT 24
Finished	Aug 14 04:30:13 PM PDT 24
Peak memory	219648 kb
Host	smart-04e0bf34-17f1-4977-a66f-976d61d74f6d
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2757832869 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.lc_ctrl_csr_mem_rw_with_rand_reset.2757832869
Directory	/workspace/12.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_csr_rw.3276155841
Short name	T50
Test name
Test status
Simulation time	32667158 ps
CPU time	0.95 seconds
Started	Aug 14 04:29:53 PM PDT 24
Finished	Aug 14 04:29:54 PM PDT 24
Peak memory	209684 kb
Host	smart-85060a19-f651-4b4b-bd97-f767fa777995
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276155841 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_csr_rw.3276155841
Directory	/workspace/12.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_same_csr_outstanding.3918640215
Short name	T37
Test name
Test status
Simulation time	26326658 ps
CPU time	1.34 seconds
Started	Aug 14 04:29:56 PM PDT 24
Finished	Aug 14 04:29:58 PM PDT 24
Peak memory	210044 kb
Host	smart-e211f5fb-fc6c-4fc2-94fa-c1d99275d107
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918640215 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctr l_same_csr_outstanding.3918640215
Directory	/workspace/12.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_errors.57598954
Short name	T30
Test name
Test status
Simulation time	1075354922 ps
CPU time	3.26 seconds
Started	Aug 14 04:30:11 PM PDT 24
Finished	Aug 14 04:30:14 PM PDT 24
Peak memory	218188 kb
Host	smart-ebb41c2b-20f9-4c10-ada2-c69ec003efce
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57598954 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_errors.57598954
Directory	/workspace/12.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/12.lc_ctrl_tl_intg_err.3143811145
Short name	T26
Test name
Test status
Simulation time	389414530 ps
CPU time	2.67 seconds
Started	Aug 14 04:30:08 PM PDT 24
Finished	Aug 14 04:30:11 PM PDT 24
Peak memory	223100 kb
Host	smart-dd3da83c-529f-4fce-8d7d-cfba4e6be37e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143811145 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.lc_ctrl_tl_intg _err.3143811145
Directory	/workspace/12.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_mem_rw_with_rand_reset.1641494972
Short name	T123
Test name
Test status
Simulation time	25928622 ps
CPU time	2.02 seconds
Started	Aug 14 04:29:59 PM PDT 24
Finished	Aug 14 04:30:01 PM PDT 24
Peak memory	219456 kb
Host	smart-b550b6a5-ed07-4393-b2de-bd346c20e535
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641494972 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.lc_ctrl_csr_mem_rw_with_rand_reset.1641494972
Directory	/workspace/13.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_csr_rw.3751803753
Short name	T47
Test name
Test status
Simulation time	12496553 ps
CPU time	0.87 seconds
Started	Aug 14 04:29:57 PM PDT 24
Finished	Aug 14 04:29:58 PM PDT 24
Peak memory	210036 kb
Host	smart-8208f2bf-af70-49af-8be7-d2dafa068f25
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751803753 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_csr_rw.3751803753
Directory	/workspace/13.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_same_csr_outstanding.2660528977
Short name	T35
Test name
Test status
Simulation time	69858389 ps
CPU time	1.21 seconds
Started	Aug 14 04:29:53 PM PDT 24
Finished	Aug 14 04:29:54 PM PDT 24
Peak memory	210028 kb
Host	smart-c156f8a2-e4ae-46e3-b00e-44fcf7fe5f9c
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660528977 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctr l_same_csr_outstanding.2660528977
Directory	/workspace/13.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/13.lc_ctrl_tl_intg_err.1897821478
Short name	T128
Test name
Test status
Simulation time	461214412 ps
CPU time	2.66 seconds
Started	Aug 14 04:29:58 PM PDT 24
Finished	Aug 14 04:30:01 PM PDT 24
Peak memory	222172 kb
Host	smart-a0153c63-50f5-4088-bc58-efcf7cb6d1d5
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897821478 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.lc_ctrl_tl_intg _err.1897821478
Directory	/workspace/13.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_mem_rw_with_rand_reset.2506379068
Short name	T118
Test name
Test status
Simulation time	45490279 ps
CPU time	1.16 seconds
Started	Aug 14 04:29:47 PM PDT 24
Finished	Aug 14 04:29:49 PM PDT 24
Peak memory	220140 kb
Host	smart-2743ebb8-f938-474f-ac28-39dd23a425b4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506379068 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 14.lc_ctrl_csr_mem_rw_with_rand_reset.2506379068
Directory	/workspace/14.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_csr_rw.2989147228
Short name	T171
Test name
Test status
Simulation time	22616219 ps
CPU time	0.84 seconds
Started	Aug 14 04:29:58 PM PDT 24
Finished	Aug 14 04:29:59 PM PDT 24
Peak memory	209780 kb
Host	smart-441df68f-0d3c-414a-a1b1-99bc11443291
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989147228 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_csr_rw.2989147228
Directory	/workspace/14.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_same_csr_outstanding.2583829428
Short name	T90
Test name
Test status
Simulation time	34813277 ps
CPU time	1.39 seconds
Started	Aug 14 04:29:53 PM PDT 24
Finished	Aug 14 04:29:55 PM PDT 24
Peak memory	210020 kb
Host	smart-1fbd3247-7188-4fbe-aed3-f45a44650dcc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583829428 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctr l_same_csr_outstanding.2583829428
Directory	/workspace/14.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_errors.251946233
Short name	T106
Test name
Test status
Simulation time	96648668 ps
CPU time	3.24 seconds
Started	Aug 14 04:30:05 PM PDT 24
Finished	Aug 14 04:30:09 PM PDT 24
Peak memory	218192 kb
Host	smart-b4a0f926-9680-4d32-aee0-2736d055213e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251946233 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_errors.251946233
Directory	/workspace/14.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/14.lc_ctrl_tl_intg_err.3827737181
Short name	T60
Test name
Test status
Simulation time	125318366 ps
CPU time	1.89 seconds
Started	Aug 14 04:30:04 PM PDT 24
Finished	Aug 14 04:30:06 PM PDT 24
Peak memory	222736 kb
Host	smart-4dc89cb2-1b48-4a56-b780-22e5c3671874
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827737181 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.lc_ctrl_tl_intg _err.3827737181
Directory	/workspace/14.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_mem_rw_with_rand_reset.917154562
Short name	T32
Test name
Test status
Simulation time	98144888 ps
CPU time	1.66 seconds
Started	Aug 14 04:29:43 PM PDT 24
Finished	Aug 14 04:29:45 PM PDT 24
Peak memory	218312 kb
Host	smart-03ebc729-35b5-4776-9a92-40194d3253b4
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917154562 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 15.lc_ctrl_csr_mem_rw_with_rand_reset.917154562
Directory	/workspace/15.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_csr_rw.1330268230
Short name	T141
Test name
Test status
Simulation time	24836792 ps
CPU time	0.89 seconds
Started	Aug 14 04:29:51 PM PDT 24
Finished	Aug 14 04:29:52 PM PDT 24
Peak memory	209772 kb
Host	smart-5e0bae6a-09bb-4e8e-9727-72d54137999c
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330268230 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_csr_rw.1330268230
Directory	/workspace/15.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/15.lc_ctrl_tl_errors.947822338
Short name	T102
Test name
Test status
Simulation time	25876283 ps
CPU time	2.07 seconds
Started	Aug 14 04:29:51 PM PDT 24
Finished	Aug 14 04:29:53 PM PDT 24
Peak memory	218392 kb
Host	smart-13e8b3f6-5c1e-4179-a4ee-a57eab8ecf46
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947822338 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.lc_ctrl_tl_errors.947822338
Directory	/workspace/15.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_mem_rw_with_rand_reset.2061623133
Short name	T150
Test name
Test status
Simulation time	35164304 ps
CPU time	1.23 seconds
Started	Aug 14 04:30:10 PM PDT 24
Finished	Aug 14 04:30:12 PM PDT 24
Peak memory	218292 kb
Host	smart-25b6d752-2c12-4557-bbdb-88f18d76884e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061623133 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 16.lc_ctrl_csr_mem_rw_with_rand_reset.2061623133
Directory	/workspace/16.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_csr_rw.1348886736
Short name	T185
Test name
Test status
Simulation time	23112917 ps
CPU time	0.89 seconds
Started	Aug 14 04:29:52 PM PDT 24
Finished	Aug 14 04:29:53 PM PDT 24
Peak memory	209872 kb
Host	smart-c3b553d6-6633-4474-9ce5-5452b825f342
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348886736 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_csr_rw.1348886736
Directory	/workspace/16.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_same_csr_outstanding.2708935851
Short name	T114
Test name
Test status
Simulation time	53248124 ps
CPU time	1 seconds
Started	Aug 14 04:30:06 PM PDT 24
Finished	Aug 14 04:30:07 PM PDT 24
Peak memory	210008 kb
Host	smart-27e558eb-92a1-4c06-87f6-0753adb3a907
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708935851 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctr l_same_csr_outstanding.2708935851
Directory	/workspace/16.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/16.lc_ctrl_tl_errors.1961086982
Short name	T110
Test name
Test status
Simulation time	30873397 ps
CPU time	1.91 seconds
Started	Aug 14 04:30:03 PM PDT 24
Finished	Aug 14 04:30:05 PM PDT 24
Peak memory	218208 kb
Host	smart-eb69bbcc-185a-49b0-8690-f5a19345c3fa
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961086982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.lc_ctrl_tl_errors.1961086982
Directory	/workspace/16.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_mem_rw_with_rand_reset.2697096990
Short name	T147
Test name
Test status
Simulation time	42735846 ps
CPU time	1.11 seconds
Started	Aug 14 04:29:47 PM PDT 24
Finished	Aug 14 04:29:48 PM PDT 24
Peak memory	220396 kb
Host	smart-4112500e-7549-4fde-9c0c-9ca5150b4061
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697096990 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.lc_ctrl_csr_mem_rw_with_rand_reset.2697096990
Directory	/workspace/17.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_csr_rw.2679422816
Short name	T122
Test name
Test status
Simulation time	16831578 ps
CPU time	1.05 seconds
Started	Aug 14 04:29:59 PM PDT 24
Finished	Aug 14 04:30:05 PM PDT 24
Peak memory	210036 kb
Host	smart-1c56aba5-d2d2-43b4-8b19-274460be5f04
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679422816 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_csr_rw.2679422816
Directory	/workspace/17.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_same_csr_outstanding.786317630
Short name	T27
Test name
Test status
Simulation time	47148912 ps
CPU time	1.94 seconds
Started	Aug 14 04:30:02 PM PDT 24
Finished	Aug 14 04:30:04 PM PDT 24
Peak memory	210000 kb
Host	smart-029d4fa3-03a4-4838-bf6f-8e9308c8a2b8
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786317630 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl _same_csr_outstanding.786317630
Directory	/workspace/17.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/17.lc_ctrl_tl_errors.1265286886
Short name	T126
Test name
Test status
Simulation time	128319427 ps
CPU time	3.29 seconds
Started	Aug 14 04:29:53 PM PDT 24
Finished	Aug 14 04:29:57 PM PDT 24
Peak memory	218220 kb
Host	smart-fc935218-9325-49ec-b79b-a6258716d2a3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265286886 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.lc_ctrl_tl_errors.1265286886
Directory	/workspace/17.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_mem_rw_with_rand_reset.1372469482
Short name	T113
Test name
Test status
Simulation time	46831207 ps
CPU time	1.28 seconds
Started	Aug 14 04:30:08 PM PDT 24
Finished	Aug 14 04:30:09 PM PDT 24
Peak memory	218376 kb
Host	smart-89b22ade-a7b4-4b00-9a79-e3efefd8b042
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372469482 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.lc_ctrl_csr_mem_rw_with_rand_reset.1372469482
Directory	/workspace/18.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_csr_rw.2251632789
Short name	T39
Test name
Test status
Simulation time	45076259 ps
CPU time	0.98 seconds
Started	Aug 14 04:29:51 PM PDT 24
Finished	Aug 14 04:29:52 PM PDT 24
Peak memory	210032 kb
Host	smart-c71060cb-7ded-4aab-8ceb-cd698218c2cd
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251632789 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_csr_rw.2251632789
Directory	/workspace/18.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_same_csr_outstanding.3298626255
Short name	T53
Test name
Test status
Simulation time	37526891 ps
CPU time	1.75 seconds
Started	Aug 14 04:30:04 PM PDT 24
Finished	Aug 14 04:30:05 PM PDT 24
Peak memory	210024 kb
Host	smart-98b4f092-d499-4215-9193-27ee52194dad
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298626255 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctr l_same_csr_outstanding.3298626255
Directory	/workspace/18.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/18.lc_ctrl_tl_errors.180511127
Short name	T156
Test name
Test status
Simulation time	41063460 ps
CPU time	2.86 seconds
Started	Aug 14 04:30:01 PM PDT 24
Finished	Aug 14 04:30:04 PM PDT 24
Peak memory	218196 kb
Host	smart-4d91a0af-9b76-46ce-8bf6-d2af22ab66ed
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180511127 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.lc_ctrl_tl_errors.180511127
Directory	/workspace/18.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_mem_rw_with_rand_reset.3065303307
Short name	T135
Test name
Test status
Simulation time	21387088 ps
CPU time	1.38 seconds
Started	Aug 14 04:30:01 PM PDT 24
Finished	Aug 14 04:30:02 PM PDT 24
Peak memory	219876 kb
Host	smart-f733ad79-9db0-405f-8a7c-66a63edb9d00
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065303307 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.lc_ctrl_csr_mem_rw_with_rand_reset.3065303307
Directory	/workspace/19.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_csr_rw.1770208276
Short name	T43
Test name
Test status
Simulation time	32861710 ps
CPU time	0.94 seconds
Started	Aug 14 04:30:03 PM PDT 24
Finished	Aug 14 04:30:04 PM PDT 24
Peak memory	209984 kb
Host	smart-dfa75b8b-833a-4b4f-8ff8-f09db9475d08
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770208276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_csr_rw.1770208276
Directory	/workspace/19.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_same_csr_outstanding.497496525
Short name	T165
Test name
Test status
Simulation time	29846605 ps
CPU time	1.25 seconds
Started	Aug 14 04:29:55 PM PDT 24
Finished	Aug 14 04:29:57 PM PDT 24
Peak memory	210040 kb
Host	smart-bdaae1a4-4e53-4a20-a20e-f26064d1580d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497496525 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl _same_csr_outstanding.497496525
Directory	/workspace/19.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/19.lc_ctrl_tl_intg_err.399153321
Short name	T16
Test name
Test status
Simulation time	46467002 ps
CPU time	1.92 seconds
Started	Aug 14 04:30:20 PM PDT 24
Finished	Aug 14 04:30:22 PM PDT 24
Peak memory	222768 kb
Host	smart-d65e3658-c36b-4265-9332-6395b7c70da2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399153321 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.lc_ctrl_tl_intg_ err.399153321
Directory	/workspace/19.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_aliasing.1581225237
Short name	T105
Test name
Test status
Simulation time	22281106 ps
CPU time	1.27 seconds
Started	Aug 14 04:30:08 PM PDT 24
Finished	Aug 14 04:30:10 PM PDT 24
Peak memory	210032 kb
Host	smart-739956a9-96f9-42b5-8489-2ab57685b5ee
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581225237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_aliasin g.1581225237
Directory	/workspace/2.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_bit_bash.1689125332
Short name	T88
Test name
Test status
Simulation time	89683976 ps
CPU time	3.05 seconds
Started	Aug 14 04:29:32 PM PDT 24
Finished	Aug 14 04:29:35 PM PDT 24
Peak memory	209984 kb
Host	smart-cab281a8-47e9-4a19-b5ee-09ea2b77d9ae
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689125332 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_bit_bas h.1689125332
Directory	/workspace/2.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_hw_reset.2298057982
Short name	T92
Test name
Test status
Simulation time	13560768 ps
CPU time	1.07 seconds
Started	Aug 14 04:29:43 PM PDT 24
Finished	Aug 14 04:29:44 PM PDT 24
Peak memory	210568 kb
Host	smart-5395f120-ede2-46b6-943c-c6d7711ac3ca
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298057982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_hw_rese t.2298057982
Directory	/workspace/2.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_mem_rw_with_rand_reset.142525595
Short name	T160
Test name
Test status
Simulation time	80424962 ps
CPU time	1.38 seconds
Started	Aug 14 04:29:52 PM PDT 24
Finished	Aug 14 04:29:54 PM PDT 24
Peak memory	222504 kb
Host	smart-e3599e22-90bf-4310-adfd-a4bd432c27d2
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142525595 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 2.lc_ctrl_csr_mem_rw_with_rand_reset.142525595
Directory	/workspace/2.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_csr_rw.160967517
Short name	T51
Test name
Test status
Simulation time	14350680 ps
CPU time	0.87 seconds
Started	Aug 14 04:29:47 PM PDT 24
Finished	Aug 14 04:29:48 PM PDT 24
Peak memory	210016 kb
Host	smart-abf14355-39b3-46fd-86ef-9cdb878e129f
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160967517 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_csr_rw.160967517
Directory	/workspace/2.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_alert_test.1328401409
Short name	T41
Test name
Test status
Simulation time	39911935 ps
CPU time	1.12 seconds
Started	Aug 14 04:29:49 PM PDT 24
Finished	Aug 14 04:29:50 PM PDT 24
Peak memory	209952 kb
Host	smart-f05e10eb-f618-43e8-852b-081ed31822a4
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328401409 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.lc_ctrl_jtag_alert_test.1328401409
Directory	/workspace/2.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_aliasing.2072179927
Short name	T97
Test name
Test status
Simulation time	375247238 ps
CPU time	5.01 seconds
Started	Aug 14 04:29:45 PM PDT 24
Finished	Aug 14 04:29:50 PM PDT 24
Peak memory	209260 kb
Host	smart-862d362e-7220-4247-a598-51919d098e4a
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072179927 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_aliasing.2072179927
Directory	/workspace/2.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_bit_bash.4273779329
Short name	T95
Test name
Test status
Simulation time	636407475 ps
CPU time	6.38 seconds
Started	Aug 14 04:29:42 PM PDT 24
Finished	Aug 14 04:29:49 PM PDT 24
Peak memory	208700 kb
Host	smart-96394d36-fe13-45e5-8140-2064f38d618c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273779329 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_bit_bash.4273779329
Directory	/workspace/2.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_hw_reset.2090571709
Short name	T80
Test name
Test status
Simulation time	1523416410 ps
CPU time	1.64 seconds
Started	Aug 14 04:29:25 PM PDT 24
Finished	Aug 14 04:29:27 PM PDT 24
Peak memory	211440 kb
Host	smart-6558d858-09e4-4ab8-8d26-dd9b41c8fbcf
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090571709 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 2.lc_ctrl_jtag_csr_hw_reset.2090571709
Directory	/workspace/2.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.868116959
Short name	T12
Test name
Test status
Simulation time	91191122 ps
CPU time	3.17 seconds
Started	Aug 14 04:29:42 PM PDT 24
Finished	Aug 14 04:29:46 PM PDT 24
Peak memory	218940 kb
Host	smart-f5c598b0-832c-42fc-b3c2-329faba63fe5
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868116 959 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.868116959
Directory	/workspace/2.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_csr_rw.1888248237
Short name	T104
Test name
Test status
Simulation time	142835553 ps
CPU time	1.5 seconds
Started	Aug 14 04:29:38 PM PDT 24
Finished	Aug 14 04:29:40 PM PDT 24
Peak memory	209988 kb
Host	smart-b1c89bed-2a5b-4490-bfef-11ad36e9a949
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888248237 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_csr_rw.1888248237
Directory	/workspace/2.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_jtag_same_csr_outstanding.273542507
Short name	T89
Test name
Test status
Simulation time	33308041 ps
CPU time	1.25 seconds
Started	Aug 14 04:29:27 PM PDT 24
Finished	Aug 14 04:29:28 PM PDT 24
Peak memory	209972 kb
Host	smart-afa05bee-8f3d-42ec-be7a-4a7ae386dacc
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273542507 -assert nopostproc +UVM_TESTNAM E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_jtag_same_csr_outstanding.273542507
Directory	/workspace/2.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_same_csr_outstanding.265504933
Short name	T34
Test name
Test status
Simulation time	226543910 ps
CPU time	1.88 seconds
Started	Aug 14 04:29:49 PM PDT 24
Finished	Aug 14 04:29:51 PM PDT 24
Peak memory	210136 kb
Host	smart-8fafdabe-de3a-4c33-af03-e6bbbee7234d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265504933 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_ same_csr_outstanding.265504933
Directory	/workspace/2.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/2.lc_ctrl_tl_errors.879103475
Short name	T121
Test name
Test status
Simulation time	182872710 ps
CPU time	2.5 seconds
Started	Aug 14 04:29:40 PM PDT 24
Finished	Aug 14 04:29:43 PM PDT 24
Peak memory	218280 kb
Host	smart-504965ab-71b1-480d-b377-db023eb2c93a
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=879103475 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.lc_ctrl_tl_errors.879103475
Directory	/workspace/2.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_aliasing.2496504764
Short name	T49
Test name
Test status
Simulation time	17223758 ps
CPU time	1.2 seconds
Started	Aug 14 04:29:55 PM PDT 24
Finished	Aug 14 04:29:56 PM PDT 24
Peak memory	209996 kb
Host	smart-83391a03-ba62-4ce2-ac78-ca181a5ccfe5
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496504764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_aliasin g.2496504764
Directory	/workspace/3.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_bit_bash.4223370463
Short name	T169
Test name
Test status
Simulation time	52071278 ps
CPU time	1.73 seconds
Started	Aug 14 04:29:29 PM PDT 24
Finished	Aug 14 04:29:30 PM PDT 24
Peak memory	209920 kb
Host	smart-f48509b2-0dcd-4774-9d5d-2ea25a76ab9d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223370463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_bit_bas h.4223370463
Directory	/workspace/3.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_hw_reset.679956416
Short name	T13
Test name
Test status
Simulation time	68545675 ps
CPU time	0.99 seconds
Started	Aug 14 04:29:50 PM PDT 24
Finished	Aug 14 04:29:52 PM PDT 24
Peak memory	212264 kb
Host	smart-65ff73bf-0953-435f-a8bd-ce290a351aa8
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679956416 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_hw_reset .679956416
Directory	/workspace/3.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_mem_rw_with_rand_reset.2793943724
Short name	T139
Test name
Test status
Simulation time	125761887 ps
CPU time	1.27 seconds
Started	Aug 14 04:29:39 PM PDT 24
Finished	Aug 14 04:29:41 PM PDT 24
Peak memory	219456 kb
Host	smart-79ee916d-09ce-423f-8ba7-f967d2fe2e69
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793943724 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.lc_ctrl_csr_mem_rw_with_rand_reset.2793943724
Directory	/workspace/3.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_csr_rw.1250760983
Short name	T45
Test name
Test status
Simulation time	31761358 ps
CPU time	0.86 seconds
Started	Aug 14 04:29:42 PM PDT 24
Finished	Aug 14 04:29:43 PM PDT 24
Peak memory	209728 kb
Host	smart-76ad3ac7-7ba9-4b14-8dee-8066febd31fb
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250760983 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_csr_rw.1250760983
Directory	/workspace/3.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_alert_test.3645172213
Short name	T161
Test name
Test status
Simulation time	199567234 ps
CPU time	1.49 seconds
Started	Aug 14 04:29:31 PM PDT 24
Finished	Aug 14 04:29:33 PM PDT 24
Peak memory	209976 kb
Host	smart-e180b78e-f1e5-425a-beba-c00f434f10ce
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645172213 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 3.lc_ctrl_jtag_alert_test.3645172213
Directory	/workspace/3.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_aliasing.3665724911
Short name	T115
Test name
Test status
Simulation time	232112455 ps
CPU time	2.99 seconds
Started	Aug 14 04:29:51 PM PDT 24
Finished	Aug 14 04:29:54 PM PDT 24
Peak memory	209332 kb
Host	smart-7eb21d13-3d3e-4bf5-91b2-390a739d5dcd
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665724911 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_aliasing.3665724911
Directory	/workspace/3.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_bit_bash.4086967296
Short name	T48
Test name
Test status
Simulation time	1374219241 ps
CPU time	31.11 seconds
Started	Aug 14 04:29:46 PM PDT 24
Finished	Aug 14 04:30:17 PM PDT 24
Peak memory	210004 kb
Host	smart-a0c7b0f2-c16d-49d8-861a-d1b4adde454f
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086967296 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_bit_bash.4086967296
Directory	/workspace/3.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_hw_reset.1257875590
Short name	T178
Test name
Test status
Simulation time	257177076 ps
CPU time	3.11 seconds
Started	Aug 14 04:29:48 PM PDT 24
Finished	Aug 14 04:29:51 PM PDT 24
Peak memory	211664 kb
Host	smart-ef524cd1-9101-4431-8769-9ffaaf6977e5
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257875590 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 3.lc_ctrl_jtag_csr_hw_reset.1257875590
Directory	/workspace/3.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2702105396
Short name	T137
Test name
Test status
Simulation time	60386802 ps
CPU time	1.34 seconds
Started	Aug 14 04:29:45 PM PDT 24
Finished	Aug 14 04:29:47 PM PDT 24
Peak memory	218332 kb
Host	smart-9c09245b-ded7-487b-ad54-a8a40a23e44b
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270210 5396 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2702105396
Directory	/workspace/3.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_csr_rw.980624642
Short name	T116
Test name
Test status
Simulation time	421697887 ps
CPU time	2.6 seconds
Started	Aug 14 04:29:32 PM PDT 24
Finished	Aug 14 04:29:34 PM PDT 24
Peak memory	210004 kb
Host	smart-e8305dfd-e86f-465d-998c-8a68c6649b99
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980624642 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_csr_rw.980624642
Directory	/workspace/3.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_jtag_same_csr_outstanding.3610425519
Short name	T127
Test name
Test status
Simulation time	21456442 ps
CPU time	1.22 seconds
Started	Aug 14 04:29:57 PM PDT 24
Finished	Aug 14 04:29:58 PM PDT 24
Peak memory	218260 kb
Host	smart-c28a18ff-7a60-44f5-adc9-a9e95f5ed4a9
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610425519 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_jtag_same_csr_outstanding.3610425519
Directory	/workspace/3.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_same_csr_outstanding.377476276
Short name	T25
Test name
Test status
Simulation time	39148406 ps
CPU time	1.68 seconds
Started	Aug 14 04:30:01 PM PDT 24
Finished	Aug 14 04:30:03 PM PDT 24
Peak memory	218236 kb
Host	smart-f5c8637e-7579-488a-a6bb-7dd5155b7d1f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377476276 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_ same_csr_outstanding.377476276
Directory	/workspace/3.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/3.lc_ctrl_tl_errors.1124257588
Short name	T103
Test name
Test status
Simulation time	426136368 ps
CPU time	3 seconds
Started	Aug 14 04:29:41 PM PDT 24
Finished	Aug 14 04:29:44 PM PDT 24
Peak memory	218212 kb
Host	smart-6f6689f2-296c-42e7-bc5f-97c9da631d7c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124257588 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.lc_ctrl_tl_errors.1124257588
Directory	/workspace/3.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_aliasing.1040643741
Short name	T42
Test name
Test status
Simulation time	17575073 ps
CPU time	1.3 seconds
Started	Aug 14 04:29:58 PM PDT 24
Finished	Aug 14 04:29:59 PM PDT 24
Peak memory	210048 kb
Host	smart-f7ecd277-30fb-4f4e-9f86-8f06e37494fa
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040643741 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_aliasin g.1040643741
Directory	/workspace/4.lc_ctrl_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_bit_bash.3325510103
Short name	T154
Test name
Test status
Simulation time	47202609 ps
CPU time	1.85 seconds
Started	Aug 14 04:29:51 PM PDT 24
Finished	Aug 14 04:29:53 PM PDT 24
Peak memory	208432 kb
Host	smart-192eb119-7633-4215-8212-02d8001dff71
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325510103 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_bit_bas h.3325510103
Directory	/workspace/4.lc_ctrl_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_hw_reset.2370719460
Short name	T44
Test name
Test status
Simulation time	29987794 ps
CPU time	1.09 seconds
Started	Aug 14 04:29:56 PM PDT 24
Finished	Aug 14 04:29:57 PM PDT 24
Peak memory	212324 kb
Host	smart-24a530b1-49b6-40d5-9f3a-fbd03e649be5
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370719460 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_hw_rese t.2370719460
Directory	/workspace/4.lc_ctrl_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_mem_rw_with_rand_reset.3203970659
Short name	T167
Test name
Test status
Simulation time	97662483 ps
CPU time	1.38 seconds
Started	Aug 14 04:29:51 PM PDT 24
Finished	Aug 14 04:29:52 PM PDT 24
Peak memory	219852 kb
Host	smart-cad83276-81c0-40eb-b63e-12ebf2b35735
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203970659 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.lc_ctrl_csr_mem_rw_with_rand_reset.3203970659
Directory	/workspace/4.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_csr_rw.2842618873
Short name	T157
Test name
Test status
Simulation time	51485664 ps
CPU time	0.97 seconds
Started	Aug 14 04:29:57 PM PDT 24
Finished	Aug 14 04:29:58 PM PDT 24
Peak memory	210028 kb
Host	smart-ba2c72c4-fbcf-4930-b6a4-b39122cc4762
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842618873 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_csr_rw.2842618873
Directory	/workspace/4.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_alert_test.1883454153
Short name	T132
Test name
Test status
Simulation time	200295703 ps
CPU time	1.13 seconds
Started	Aug 14 04:29:58 PM PDT 24
Finished	Aug 14 04:29:59 PM PDT 24
Peak memory	210000 kb
Host	smart-7eeb3ef1-9470-420f-9230-7134033cb1ac
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883454153 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 4.lc_ctrl_jtag_alert_test.1883454153
Directory	/workspace/4.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_aliasing.4111421463
Short name	T100
Test name
Test status
Simulation time	582477177 ps
CPU time	6.09 seconds
Started	Aug 14 04:29:53 PM PDT 24
Finished	Aug 14 04:29:59 PM PDT 24
Peak memory	209900 kb
Host	smart-eac1cb61-4f80-4751-8a87-fdafe131ba72
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111421463 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 4.lc_ctrl_jtag_csr_aliasing.4111421463
Directory	/workspace/4.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_bit_bash.693332089
Short name	T144
Test name
Test status
Simulation time	2512839576 ps
CPU time	5.87 seconds
Started	Aug 14 04:29:42 PM PDT 24
Finished	Aug 14 04:29:48 PM PDT 24
Peak memory	210244 kb
Host	smart-dd6be845-2da9-4cd0-b1a7-def00c20d6f1
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693332089 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 4.lc_ctrl_jtag_csr_bit_bash.693332089
Directory	/workspace/4.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_hw_reset.593835299
Short name	T175
Test name
Test status
Simulation time	230236010 ps
CPU time	1.82 seconds
Started	Aug 14 04:29:32 PM PDT 24
Finished	Aug 14 04:29:34 PM PDT 24
Peak memory	211692 kb
Host	smart-77d4118d-2099-47ff-9588-8f1bea8d6fea
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593835299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 4.lc_ctrl_jtag_csr_hw_reset.593835299
Directory	/workspace/4.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1932051545
Short name	T176
Test name
Test status
Simulation time	54194516 ps
CPU time	1.99 seconds
Started	Aug 14 04:29:49 PM PDT 24
Finished	Aug 14 04:29:51 PM PDT 24
Peak memory	218360 kb
Host	smart-da813914-461f-4f8d-9ec2-453e59bd7652
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193205 1545 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1932051545
Directory	/workspace/4.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_csr_rw.2561042786
Short name	T69
Test name
Test status
Simulation time	34937702 ps
CPU time	1.52 seconds
Started	Aug 14 04:29:52 PM PDT 24
Finished	Aug 14 04:29:53 PM PDT 24
Peak memory	210028 kb
Host	smart-96da274e-8c24-411d-9fa4-1e391ac9ff10
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561042786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_csr_rw.2561042786
Directory	/workspace/4.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_jtag_same_csr_outstanding.762788891
Short name	T180
Test name
Test status
Simulation time	16974636 ps
CPU time	0.95 seconds
Started	Aug 14 04:29:49 PM PDT 24
Finished	Aug 14 04:29:50 PM PDT 24
Peak memory	210040 kb
Host	smart-ba4e8257-a4dd-451a-b258-b8fd67930746
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762788891 -assert nopostproc +UVM_TESTNAM E=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_jtag_same_csr_outstanding.762788891
Directory	/workspace/4.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_same_csr_outstanding.2206035315
Short name	T2
Test name
Test status
Simulation time	72881854 ps
CPU time	1.15 seconds
Started	Aug 14 04:29:47 PM PDT 24
Finished	Aug 14 04:29:49 PM PDT 24
Peak memory	210036 kb
Host	smart-d7896331-7ce9-4863-89f8-e96f688cdfd6
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206035315 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl _same_csr_outstanding.2206035315
Directory	/workspace/4.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/4.lc_ctrl_tl_errors.3744796575
Short name	T59
Test name
Test status
Simulation time	288227298 ps
CPU time	4.89 seconds
Started	Aug 14 04:29:56 PM PDT 24
Finished	Aug 14 04:30:01 PM PDT 24
Peak memory	218348 kb
Host	smart-2b4d4c62-e748-4076-a175-3869ee3ad174
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744796575 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.lc_ctrl_tl_errors.3744796575
Directory	/workspace/4.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_mem_rw_with_rand_reset.824723021
Short name	T181
Test name
Test status
Simulation time	27459540 ps
CPU time	1.82 seconds
Started	Aug 14 04:29:42 PM PDT 24
Finished	Aug 14 04:29:46 PM PDT 24
Peak memory	226404 kb
Host	smart-bf71923b-46ef-47a9-a798-f1245c77dbe9
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824723021 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 5.lc_ctrl_csr_mem_rw_with_rand_reset.824723021
Directory	/workspace/5.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_csr_rw.3489459151
Short name	T40
Test name
Test status
Simulation time	235043298 ps
CPU time	0.84 seconds
Started	Aug 14 04:29:25 PM PDT 24
Finished	Aug 14 04:29:26 PM PDT 24
Peak memory	210020 kb
Host	smart-489878c3-6912-4823-897c-36840996c2e3
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489459151 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_csr_rw.3489459151
Directory	/workspace/5.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_alert_test.1141896855
Short name	T18
Test name
Test status
Simulation time	720793657 ps
CPU time	2.83 seconds
Started	Aug 14 04:29:54 PM PDT 24
Finished	Aug 14 04:29:56 PM PDT 24
Peak memory	210008 kb
Host	smart-1c9cf232-df48-4321-a3a5-f7aba2b175b4
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141896855 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 5.lc_ctrl_jtag_alert_test.1141896855
Directory	/workspace/5.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_aliasing.3730400019
Short name	T8
Test name
Test status
Simulation time	2716739948 ps
CPU time	28.21 seconds
Started	Aug 14 04:29:49 PM PDT 24
Finished	Aug 14 04:30:17 PM PDT 24
Peak memory	209444 kb
Host	smart-c9f4ff38-5a0a-4bfd-8b16-76bee230e2e1
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730400019 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_aliasing.3730400019
Directory	/workspace/5.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_bit_bash.2276876275
Short name	T162
Test name
Test status
Simulation time	3588051578 ps
CPU time	9.65 seconds
Started	Aug 14 04:29:25 PM PDT 24
Finished	Aug 14 04:29:35 PM PDT 24
Peak memory	210084 kb
Host	smart-383a9115-9c09-4186-a8da-bc3014fede68
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276876275 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_bit_bash.2276876275
Directory	/workspace/5.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_hw_reset.1352188665
Short name	T101
Test name
Test status
Simulation time	82687398 ps
CPU time	2.74 seconds
Started	Aug 14 04:29:49 PM PDT 24
Finished	Aug 14 04:29:52 PM PDT 24
Peak memory	211740 kb
Host	smart-42d13039-b5a7-48f6-b09d-ae809fdb6658
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352188665 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 5.lc_ctrl_jtag_csr_hw_reset.1352188665
Directory	/workspace/5.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3998692910
Short name	T184
Test name
Test status
Simulation time	148289379 ps
CPU time	2.64 seconds
Started	Aug 14 04:29:32 PM PDT 24
Finished	Aug 14 04:29:35 PM PDT 24
Peak memory	218348 kb
Host	smart-935b6aa3-4e24-4196-805e-20302f34aad3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399869 2910 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3998692910
Directory	/workspace/5.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_csr_rw.3947385317
Short name	T68
Test name
Test status
Simulation time	90131618 ps
CPU time	2.55 seconds
Started	Aug 14 04:29:47 PM PDT 24
Finished	Aug 14 04:29:49 PM PDT 24
Peak memory	209948 kb
Host	smart-e9e2284b-f941-4526-ac7d-0cc5d4c10e8d
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947385317 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_csr_rw.3947385317
Directory	/workspace/5.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_jtag_same_csr_outstanding.2472969688
Short name	T129
Test name
Test status
Simulation time	36578938 ps
CPU time	1.23 seconds
Started	Aug 14 04:29:38 PM PDT 24
Finished	Aug 14 04:29:39 PM PDT 24
Peak memory	210032 kb
Host	smart-12cea173-5892-4c73-81f8-52fe3b89928f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472969688 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_jtag_same_csr_outstanding.2472969688
Directory	/workspace/5.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_same_csr_outstanding.2759435235
Short name	T117
Test name
Test status
Simulation time	40092594 ps
CPU time	1.42 seconds
Started	Aug 14 04:29:55 PM PDT 24
Finished	Aug 14 04:29:57 PM PDT 24
Peak memory	212140 kb
Host	smart-2b5c26c5-c79d-44fb-abb7-bebda4b661fd
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759435235 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl _same_csr_outstanding.2759435235
Directory	/workspace/5.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_errors.2964546656
Short name	T54
Test name
Test status
Simulation time	25433997 ps
CPU time	1.69 seconds
Started	Aug 14 04:29:50 PM PDT 24
Finished	Aug 14 04:29:51 PM PDT 24
Peak memory	218244 kb
Host	smart-385158e3-3f66-4ad5-b77c-657575d0cba8
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964546656 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_errors.2964546656
Directory	/workspace/5.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/5.lc_ctrl_tl_intg_err.594560700
Short name	T17
Test name
Test status
Simulation time	203539777 ps
CPU time	2.78 seconds
Started	Aug 14 04:29:57 PM PDT 24
Finished	Aug 14 04:30:00 PM PDT 24
Peak memory	222996 kb
Host	smart-25c24ef3-030a-47c3-ba8a-ef75d77752cc
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594560700 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_comm on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.lc_ctrl_tl_intg_e rr.594560700
Directory	/workspace/5.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_mem_rw_with_rand_reset.3080641571
Short name	T84
Test name
Test status
Simulation time	32051373 ps
CPU time	1.67 seconds
Started	Aug 14 04:29:59 PM PDT 24
Finished	Aug 14 04:30:01 PM PDT 24
Peak memory	218384 kb
Host	smart-34824dc6-f203-49b1-b159-d9a85ca6a63e
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080641571 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.lc_ctrl_csr_mem_rw_with_rand_reset.3080641571
Directory	/workspace/6.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_csr_rw.3173034764
Short name	T33
Test name
Test status
Simulation time	18844003 ps
CPU time	0.92 seconds
Started	Aug 14 04:29:40 PM PDT 24
Finished	Aug 14 04:29:46 PM PDT 24
Peak memory	210032 kb
Host	smart-2e0d547f-de5b-416e-b7a5-2c488a8a015e
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173034764 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_csr_rw.3173034764
Directory	/workspace/6.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_alert_test.601856027
Short name	T10
Test name
Test status
Simulation time	61531871 ps
CPU time	1.18 seconds
Started	Aug 14 04:29:52 PM PDT 24
Finished	Aug 14 04:29:53 PM PDT 24
Peak memory	209988 kb
Host	smart-5c1ff4a3-b002-45f5-a1fd-997528107d03
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601856027 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 6.lc_ctrl_jtag_alert_test.601856027
Directory	/workspace/6.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_bit_bash.2119359262
Short name	T151
Test name
Test status
Simulation time	5118715299 ps
CPU time	8.9 seconds
Started	Aug 14 04:29:47 PM PDT 24
Finished	Aug 14 04:29:55 PM PDT 24
Peak memory	210152 kb
Host	smart-763749e9-a3f4-48a7-a274-a46054e62f38
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119359262 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_bit_bash.2119359262
Directory	/workspace/6.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_hw_reset.1825750268
Short name	T145
Test name
Test status
Simulation time	89859616 ps
CPU time	1.27 seconds
Started	Aug 14 04:30:07 PM PDT 24
Finished	Aug 14 04:30:18 PM PDT 24
Peak memory	211508 kb
Host	smart-18b5f2d3-4071-479c-b29d-d0c2e8e4520b
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825750268 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 6.lc_ctrl_jtag_csr_hw_reset.1825750268
Directory	/workspace/6.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1880600501
Short name	T148
Test name
Test status
Simulation time	734806856 ps
CPU time	5.15 seconds
Started	Aug 14 04:29:24 PM PDT 24
Finished	Aug 14 04:29:29 PM PDT 24
Peak memory	219720 kb
Host	smart-ff14fe4a-581e-48d0-889a-10526068f070
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188060 0501 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.1880600501
Directory	/workspace/6.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_csr_rw.1268970450
Short name	T124
Test name
Test status
Simulation time	303424943 ps
CPU time	1.55 seconds
Started	Aug 14 04:29:42 PM PDT 24
Finished	Aug 14 04:29:44 PM PDT 24
Peak memory	209972 kb
Host	smart-80c95f31-f592-4736-b839-cab4e9eb25f7
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268970450 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_csr_rw.1268970450
Directory	/workspace/6.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_jtag_same_csr_outstanding.3836857176
Short name	T73
Test name
Test status
Simulation time	74040044 ps
CPU time	0.96 seconds
Started	Aug 14 04:29:39 PM PDT 24
Finished	Aug 14 04:29:40 PM PDT 24
Peak memory	210064 kb
Host	smart-03a98206-f054-4d94-afea-52c5d9e67747
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3836857176 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_jtag_same_csr_outstanding.3836857176
Directory	/workspace/6.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/6.lc_ctrl_tl_errors.1694624100
Short name	T168
Test name
Test status
Simulation time	46948305 ps
CPU time	3.05 seconds
Started	Aug 14 04:29:46 PM PDT 24
Finished	Aug 14 04:29:49 PM PDT 24
Peak memory	219216 kb
Host	smart-08d51c86-4532-4788-b595-13c2f7d7842c
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694624100 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.lc_ctrl_tl_errors.1694624100
Directory	/workspace/6.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_mem_rw_with_rand_reset.320938591
Short name	T77
Test name
Test status
Simulation time	46816420 ps
CPU time	1.72 seconds
Started	Aug 14 04:29:51 PM PDT 24
Finished	Aug 14 04:29:53 PM PDT 24
Peak memory	220200 kb
Host	smart-9bbe4adf-1c3d-457e-82c3-c73fb9852efc
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320938591 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 7.lc_ctrl_csr_mem_rw_with_rand_reset.320938591
Directory	/workspace/7.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_csr_rw.2310534129
Short name	T99
Test name
Test status
Simulation time	11459536 ps
CPU time	0.99 seconds
Started	Aug 14 04:29:53 PM PDT 24
Finished	Aug 14 04:29:54 PM PDT 24
Peak memory	210024 kb
Host	smart-9311a9fc-0216-4b95-8403-5716919f9ac9
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310534129 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_csr_rw.2310534129
Directory	/workspace/7.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_alert_test.653021698
Short name	T119
Test name
Test status
Simulation time	50143680 ps
CPU time	1.79 seconds
Started	Aug 14 04:29:28 PM PDT 24
Finished	Aug 14 04:29:30 PM PDT 24
Peak memory	210044 kb
Host	smart-04508dd5-0011-4b85-a94a-d0a96c959197
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653021698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 7.lc_ctrl_jtag_alert_test.653021698
Directory	/workspace/7.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_aliasing.648964587
Short name	T67
Test name
Test status
Simulation time	192148885 ps
CPU time	2.97 seconds
Started	Aug 14 04:29:50 PM PDT 24
Finished	Aug 14 04:29:53 PM PDT 24
Peak memory	209792 kb
Host	smart-7b4f51cc-3fa5-4a7d-bf31-5dbc7837651e
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648964587 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 7.lc_ctrl_jtag_csr_aliasing.648964587
Directory	/workspace/7.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_bit_bash.1399079663
Short name	T85
Test name
Test status
Simulation time	1185253513 ps
CPU time	6.54 seconds
Started	Aug 14 04:29:41 PM PDT 24
Finished	Aug 14 04:29:47 PM PDT 24
Peak memory	209820 kb
Host	smart-63c13a64-f5c8-494c-9712-43dd03d39fad
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399079663 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_bit_bash.1399079663
Directory	/workspace/7.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_hw_reset.3643145982
Short name	T14
Test name
Test status
Simulation time	2527507282 ps
CPU time	3.79 seconds
Started	Aug 14 04:29:54 PM PDT 24
Finished	Aug 14 04:29:58 PM PDT 24
Peak memory	211872 kb
Host	smart-851eb06a-5c4d-496c-8c8d-3cac7fe1bc57
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643145982 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 7.lc_ctrl_jtag_csr_hw_reset.3643145982
Directory	/workspace/7.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_csr_rw.1457638299
Short name	T111
Test name
Test status
Simulation time	35779751 ps
CPU time	1.02 seconds
Started	Aug 14 04:29:57 PM PDT 24
Finished	Aug 14 04:29:59 PM PDT 24
Peak memory	208752 kb
Host	smart-97a1df12-396c-4e8c-805f-d04b5ae59065
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457638299 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_te st +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_csr_rw.1457638299
Directory	/workspace/7.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_jtag_same_csr_outstanding.2408261858
Short name	T146
Test name
Test status
Simulation time	126201159 ps
CPU time	1.14 seconds
Started	Aug 14 04:29:30 PM PDT 24
Finished	Aug 14 04:29:31 PM PDT 24
Peak memory	209964 kb
Host	smart-4739ac43-039f-4055-bee9-990ac9f0766d
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408261858 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_jtag_same_csr_outstanding.2408261858
Directory	/workspace/7.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_same_csr_outstanding.3058380003
Short name	T166
Test name
Test status
Simulation time	40094869 ps
CPU time	1.54 seconds
Started	Aug 14 04:29:47 PM PDT 24
Finished	Aug 14 04:29:48 PM PDT 24
Peak memory	212128 kb
Host	smart-d94e8a5a-aff6-4631-b157-e55ef8fe3472
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058380003 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl _same_csr_outstanding.3058380003
Directory	/workspace/7.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/7.lc_ctrl_tl_errors.3630897474
Short name	T94
Test name
Test status
Simulation time	96546751 ps
CPU time	1.65 seconds
Started	Aug 14 04:29:42 PM PDT 24
Finished	Aug 14 04:29:43 PM PDT 24
Peak memory	219204 kb
Host	smart-a488b30c-5cbe-4b81-abd5-ffee31ce5694
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630897474 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.lc_ctrl_tl_errors.3630897474
Directory	/workspace/7.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_mem_rw_with_rand_reset.200952504
Short name	T96
Test name
Test status
Simulation time	106146397 ps
CPU time	1.46 seconds
Started	Aug 14 04:30:06 PM PDT 24
Finished	Aug 14 04:30:08 PM PDT 24
Peak memory	218316 kb
Host	smart-2df46efc-28e0-497b-ab8c-2570694a8f24
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200952504 -assert nopostproc +UVM_TESTNAME= lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 8.lc_ctrl_csr_mem_rw_with_rand_reset.200952504
Directory	/workspace/8.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_csr_rw.3489570284
Short name	T140
Test name
Test status
Simulation time	32729162 ps
CPU time	0.9 seconds
Started	Aug 14 04:29:32 PM PDT 24
Finished	Aug 14 04:29:33 PM PDT 24
Peak memory	210024 kb
Host	smart-cd963a69-0abb-40d8-b152-d5694635aec6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489570284 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_csr_rw.3489570284
Directory	/workspace/8.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_alert_test.113673798
Short name	T134
Test name
Test status
Simulation time	31777762 ps
CPU time	0.86 seconds
Started	Aug 14 04:29:42 PM PDT 24
Finished	Aug 14 04:29:43 PM PDT 24
Peak memory	208692 kb
Host	smart-6d8166e8-6d27-4773-b956-f710ab440961
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113673798 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /d ev/null -cm_name 8.lc_ctrl_jtag_alert_test.113673798
Directory	/workspace/8.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_aliasing.3247051161
Short name	T133
Test name
Test status
Simulation time	632628867 ps
CPU time	7.12 seconds
Started	Aug 14 04:29:39 PM PDT 24
Finished	Aug 14 04:29:47 PM PDT 24
Peak memory	210016 kb
Host	smart-0fda1880-5630-4825-987f-3dc4f0239055
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247051161 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_aliasing.3247051161
Directory	/workspace/8.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_bit_bash.3627409355
Short name	T153
Test name
Test status
Simulation time	4131267536 ps
CPU time	19.13 seconds
Started	Aug 14 04:29:54 PM PDT 24
Finished	Aug 14 04:30:13 PM PDT 24
Peak memory	210152 kb
Host	smart-8017874d-d6d4-45bd-9049-994609b6131d
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627409355 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_bit_bash.3627409355
Directory	/workspace/8.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_hw_reset.2443614734
Short name	T81
Test name
Test status
Simulation time	93703546 ps
CPU time	2.49 seconds
Started	Aug 14 04:29:37 PM PDT 24
Finished	Aug 14 04:29:40 PM PDT 24
Peak memory	211824 kb
Host	smart-3293d3cc-bbee-40f6-8d7c-11ea55513193
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2443614734 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 8.lc_ctrl_jtag_csr_hw_reset.2443614734
Directory	/workspace/8.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2230037862
Short name	T131
Test name
Test status
Simulation time	351932553 ps
CPU time	2.63 seconds
Started	Aug 14 04:29:42 PM PDT 24
Finished	Aug 14 04:29:45 PM PDT 24
Peak memory	219392 kb
Host	smart-30fb7c25-d00d-4512-b679-91ec605d93b7
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223003 7862 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.2230037862
Directory	/workspace/8.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_csr_rw.615653078
Short name	T149
Test name
Test status
Simulation time	134559082 ps
CPU time	1.99 seconds
Started	Aug 14 04:29:50 PM PDT 24
Finished	Aug 14 04:29:57 PM PDT 24
Peak memory	209932 kb
Host	smart-0f972fce-c318-4e48-9f88-0582ba00fe31
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615653078 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_csr_rw.615653078
Directory	/workspace/8.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_jtag_same_csr_outstanding.3839886826
Short name	T86
Test name
Test status
Simulation time	32898275 ps
CPU time	1.17 seconds
Started	Aug 14 04:29:40 PM PDT 24
Finished	Aug 14 04:29:41 PM PDT 24
Peak memory	210116 kb
Host	smart-ccd6ddb8-e200-47bd-8c4f-fadd0fb5f18f
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839886826 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_jtag_same_csr_outstanding.3839886826
Directory	/workspace/8.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_same_csr_outstanding.1988053899
Short name	T87
Test name
Test status
Simulation time	21264354 ps
CPU time	1.37 seconds
Started	Aug 14 04:29:47 PM PDT 24
Finished	Aug 14 04:29:49 PM PDT 24
Peak memory	212152 kb
Host	smart-cda43253-5719-4f3c-8604-f2ea597e183e
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988053899 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl _same_csr_outstanding.1988053899
Directory	/workspace/8.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_errors.471363698
Short name	T91
Test name
Test status
Simulation time	1140661094 ps
CPU time	4.8 seconds
Started	Aug 14 04:30:03 PM PDT 24
Finished	Aug 14 04:30:08 PM PDT 24
Peak memory	218232 kb
Host	smart-2e4e787f-3438-43a9-83cf-d3faae97baf3
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471363698 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_errors.471363698
Directory	/workspace/8.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/8.lc_ctrl_tl_intg_err.1873679101
Short name	T22
Test name
Test status
Simulation time	55661147 ps
CPU time	1.95 seconds
Started	Aug 14 04:29:51 PM PDT 24
Finished	Aug 14 04:29:53 PM PDT 24
Peak memory	222724 kb
Host	smart-1e52a684-907b-49b6-a932-e8c4e5de393e
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873679101 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.lc_ctrl_tl_intg_ err.1873679101
Directory	/workspace/8.lc_ctrl_tl_intg_err/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_mem_rw_with_rand_reset.1950151587
Short name	T93
Test name
Test status
Simulation time	22986413 ps
CPU time	1.39 seconds
Started	Aug 14 04:30:14 PM PDT 24
Finished	Aug 14 04:30:15 PM PDT 24
Peak memory	218260 kb
Host	smart-df0d7cfb-26c2-4507-93f8-f6e086883e39
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950151587 -assert nopostproc +UVM_TESTNAME =lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.lc_ctrl_csr_mem_rw_with_rand_reset.1950151587
Directory	/workspace/9.lc_ctrl_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_csr_rw.453731786
Short name	T46
Test name
Test status
Simulation time	18290155 ps
CPU time	1.12 seconds
Started	Aug 14 04:30:02 PM PDT 24
Finished	Aug 14 04:30:03 PM PDT 24
Peak memory	210028 kb
Host	smart-1c0d21fb-3029-4a7f-a92d-703cb72f7bd6
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/ mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453731786 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_csr_rw.453731786
Directory	/workspace/9.lc_ctrl_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_alert_test.2900225911
Short name	T109
Test name
Test status
Simulation time	68230843 ps
CPU time	1.48 seconds
Started	Aug 14 04:30:03 PM PDT 24
Finished	Aug 14 04:30:05 PM PDT 24
Peak memory	210000 kb
Host	smart-2e07a032-b7bf-40c4-be65-7dcb6586de4e
User	root
Command	/workspace/cover_reg_top/simv +run_alert_test +en_scb=0 +jtag_csr=1 +create_jtag_riscv_map=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2900225911 -assert nopostproc +UVM_TESTNAME=lc_ctrl _base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 9.lc_ctrl_jtag_alert_test.2900225911
Directory	/workspace/9.lc_ctrl_jtag_alert_test/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_aliasing.907666648
Short name	T29
Test name
Test status
Simulation time	1876061544 ps
CPU time	11.56 seconds
Started	Aug 14 04:29:50 PM PDT 24
Finished	Aug 14 04:30:02 PM PDT 24
Peak memory	209864 kb
Host	smart-ffe85854-adc9-4f03-9c67-761048ba85ff
User	root
Command	/workspace/cover_reg_top/simv +csr_aliasing +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=907666648 -assert nopostproc +UVM_TESTNAME=lc_ctrl_ba se_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev /null -cm_name 9.lc_ctrl_jtag_csr_aliasing.907666648
Directory	/workspace/9.lc_ctrl_jtag_csr_aliasing/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_bit_bash.3947580125
Short name	T82
Test name
Test status
Simulation time	2900647518 ps
CPU time	15.12 seconds
Started	Aug 14 04:30:02 PM PDT 24
Finished	Aug 14 04:30:17 PM PDT 24
Peak memory	210112 kb
Host	smart-90bf964d-5389-45d0-8da4-089f47a49e7c
User	root
Command	/workspace/cover_reg_top/simv +csr_bit_bash +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947580125 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.lc_ctrl_jtag_csr_bit_bash.3947580125
Directory	/workspace/9.lc_ctrl_jtag_csr_bit_bash/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_hw_reset.3464551047
Short name	T11
Test name
Test status
Simulation time	208300997 ps
CPU time	4.22 seconds
Started	Aug 14 04:29:56 PM PDT 24
Finished	Aug 14 04:30:00 PM PDT 24
Peak memory	211880 kb
Host	smart-c3cd40b9-13d4-4c70-800d-560937ed81f6
User	root
Command	/workspace/cover_reg_top/simv +csr_hw_reset +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464551047 -assert nopostproc +UVM_TESTNAME=lc_ctrl_b ase_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /de v/null -cm_name 9.lc_ctrl_jtag_csr_hw_reset.3464551047
Directory	/workspace/9.lc_ctrl_jtag_csr_hw_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3602749617
Short name	T120
Test name
Test status
Simulation time	452725984 ps
CPU time	2.1 seconds
Started	Aug 14 04:30:04 PM PDT 24
Finished	Aug 14 04:30:06 PM PDT 24
Peak memory	218304 kb
Host	smart-d2f4dce5-8619-4865-ba42-15188be1f2c3
User	root
Command	/workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360274 9617 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset.3602749617
Directory	/workspace/9.lc_ctrl_jtag_csr_mem_rw_with_rand_reset/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_csr_rw.141806839
Short name	T158
Test name
Test status
Simulation time	91726571 ps
CPU time	1.77 seconds
Started	Aug 14 04:29:37 PM PDT 24
Finished	Aug 14 04:29:39 PM PDT 24
Peak memory	210008 kb
Host	smart-f0a2a7ca-faf4-4185-a9e4-d8c9e21efd91
User	root
Command	/workspace/cover_reg_top/simv +csr_rw +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UV M_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141806839 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_tes t +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_csr_rw.141806839
Directory	/workspace/9.lc_ctrl_jtag_csr_rw/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_jtag_same_csr_outstanding.3330727611
Short name	T142
Test name
Test status
Simulation time	37483242 ps
CPU time	1.35 seconds
Started	Aug 14 04:29:44 PM PDT 24
Finished	Aug 14 04:29:45 PM PDT 24
Peak memory	212136 kb
Host	smart-ad712ca2-bd70-4f67-a3a5-a82e423635b0
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +jtag_csr=1 +create_jtag_riscv_map=1 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330727611 -assert nopostproc +UVM_TESTNA ME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_jtag_same_csr_outstanding.3330727611
Directory	/workspace/9.lc_ctrl_jtag_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_same_csr_outstanding.2811074085
Short name	T74
Test name
Test status
Simulation time	22630987 ps
CPU time	1.27 seconds
Started	Aug 14 04:30:08 PM PDT 24
Finished	Aug 14 04:30:10 PM PDT 24
Peak memory	212084 kb
Host	smart-0c1e2792-ce40-4d81-af74-df1dcd6d3802
User	root
Command	/workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811074085 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc _ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl _same_csr_outstanding.2811074085
Directory	/workspace/9.lc_ctrl_same_csr_outstanding/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_errors.3907881634
Short name	T78
Test name
Test status
Simulation time	863121016 ps
CPU time	3.04 seconds
Started	Aug 14 04:29:59 PM PDT 24
Finished	Aug 14 04:30:07 PM PDT 24
Peak memory	219292 kb
Host	smart-ba13a0b6-74da-401c-a140-405cc2f9f6f2
User	root
Command	/workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt /repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907881634 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_common_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_errors.3907881634
Directory	/workspace/9.lc_ctrl_tl_errors/latest

Test location	/workspace/coverage/cover_reg_top/9.lc_ctrl_tl_intg_err.3394964604
Short name	T79
Test name
Test status
Simulation time	76523784 ps
CPU time	2.2 seconds
Started	Aug 14 04:29:59 PM PDT 24
Finished	Aug 14 04:30:02 PM PDT 24
Peak memory	222204 kb
Host	smart-0876aa98-b996-4ba1-9352-086fa3820505
User	root
Command	/workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394964604 -assert nopostproc +UVM_TESTNAME=lc_ctrl_base_test +UVM_TEST_SEQ=lc_ctrl_com mon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.lc_ctrl_tl_intg_ err.3394964604
Directory	/workspace/9.lc_ctrl_tl_intg_err/latest