Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	858748	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1049899

1

T1

13

T2

229

T3

1741

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1609407	1			T1	11		T2	293		T3	2272
values[0x0]	149145	1			T1	2		T2	139		T3	339
values[0x1]	150095	1			T1	7		T2	152		T3	381

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	679776	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1228871

1

T1

15

T2

280

T3

2015

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6202	1			T1	1		T4	3		T11	19
valid_sources[0x01]	7631	1			T4	3		T5	4		T8	4
valid_sources[0x02]	9644	1			T4	2		T5	2		T10	3554
valid_sources[0x03]	5765	1			T4	1		T7	2		T8	1
valid_sources[0x04]	5749	1			T4	3		T5	5		T11	1
valid_sources[0x05]	5375	1			T4	1		T5	8		T15	7
valid_sources[0x06]	6102	1			T4	8		T5	2		T7	1
valid_sources[0x07]	5435	1			T6	1		T4	4		T5	3
valid_sources[0x08]	5462	1			T4	1		T9	1		T16	7
valid_sources[0x09]	5755	1			T11	2		T7	2		T8	1
valid_sources[0x0a]	6589	1			T4	4		T5	5		T7	4
valid_sources[0x0b]	22169	1			T4	1		T5	3		T11	3
valid_sources[0x0c]	6059	1			T4	4		T5	4		T11	4
valid_sources[0x0d]	5174	1			T4	2		T5	1		T7	2
valid_sources[0x0e]	5298	1			T4	6		T5	2		T11	2
valid_sources[0x0f]	6130	1			T4	2		T5	1		T11	1
valid_sources[0x10]	8956	1			T3	2992		T4	1		T5	3
valid_sources[0x11]	5850	1			T4	6		T5	3		T16	6
valid_sources[0x12]	5908	1			T4	2		T5	1		T7	1
valid_sources[0x13]	8641	1			T4	2		T5	1		T11	1
valid_sources[0x14]	9281	1			T4	6		T5	4		T8	2
valid_sources[0x15]	8568	1			T4	3		T5	3		T11	1
valid_sources[0x16]	7187	1			T4	5		T5	1		T11	10
valid_sources[0x17]	5776	1			T4	5		T5	3		T8	1
valid_sources[0x18]	6037	1			T4	2		T7	1		T8	1
valid_sources[0x19]	6326	1			T4	2		T5	4		T11	1
valid_sources[0x1a]	5821	1			T4	4		T11	3		T7	3
valid_sources[0x1b]	5732	1			T4	2		T5	1		T15	14
valid_sources[0x1c]	5849	1			T4	3		T5	1		T15	32
valid_sources[0x1d]	5714	1			T4	2		T5	3		T11	1
valid_sources[0x1e]	14296	1			T4	3		T5	3		T7	2
valid_sources[0x1f]	6186	1			T4	3		T5	4		T11	2
valid_sources[0x20]	7369	1			T4	3		T5	1		T8	5
valid_sources[0x21]	5583	1			T4	3		T8	1		T15	14
valid_sources[0x22]	5941	1			T4	2		T5	1		T11	2
valid_sources[0x23]	10383	1			T4	2		T5	1		T7	2
valid_sources[0x24]	5639	1			T4	1		T5	3		T8	1
valid_sources[0x25]	37027	1			T4	1		T5	2		T7	1
valid_sources[0x26]	9898	1			T4	4		T5	3		T8	2
valid_sources[0x27]	5857	1			T4	3		T5	3		T14	25
valid_sources[0x28]	5684	1			T4	8		T5	1		T11	3
valid_sources[0x29]	5303	1			T4	3		T5	1		T11	7
valid_sources[0x2a]	6130	1			T4	3		T5	1		T14	15
valid_sources[0x2b]	7494	1			T6	3		T4	1		T7	1
valid_sources[0x2c]	7121	1			T4	6		T5	2		T8	2
valid_sources[0x2d]	5760	1			T4	6		T5	3		T11	1
valid_sources[0x2e]	5738	1			T6	5		T4	6		T7	2
valid_sources[0x2f]	6376	1			T4	4		T11	4		T8	2
valid_sources[0x30]	6276	1			T4	3		T5	2		T7	3
valid_sources[0x31]	28832	1			T4	3		T5	1		T10	30
valid_sources[0x32]	6536	1			T4	9		T11	1		T7	4
valid_sources[0x33]	5410	1			T4	9		T11	1		T7	1
valid_sources[0x34]	5854	1			T4	3		T7	1		T8	1
valid_sources[0x35]	5725	1			T4	4		T5	4		T8	1
valid_sources[0x36]	6384	1			T4	2		T5	3		T11	1
valid_sources[0x37]	5711	1			T4	2		T7	2		T8	1
valid_sources[0x38]	5244	1			T4	3		T5	2		T11	1
valid_sources[0x39]	5692	1			T4	1		T5	2		T7	2
valid_sources[0x3a]	5460	1			T4	2		T15	5		T9	4
valid_sources[0x3b]	22331	1			T4	2		T5	1		T11	5
valid_sources[0x3c]	6617	1			T4	2		T11	6		T7	3
valid_sources[0x3d]	5923	1			T5	1		T14	20		T15	7
valid_sources[0x3e]	8031	1			T4	2		T7	1		T8	1
valid_sources[0x3f]	11362	1			T4	2		T5	2		T11	3
valid_sources[0x40]	6998	1			T4	1		T5	1		T8	2
valid_sources[0x41]	17784	1			T4	5		T5	6		T7	3
valid_sources[0x42]	5490	1			T7	3		T9	1		T16	6
valid_sources[0x43]	6510	1			T4	5		T7	1		T8	1
valid_sources[0x44]	10377	1			T4	6		T5	3		T11	2
valid_sources[0x45]	10887	1			T6	6		T4	2		T11	5
valid_sources[0x46]	7849	1			T5	1		T11	7		T13	1092
valid_sources[0x47]	5570	1			T4	5		T8	6		T15	7
valid_sources[0x48]	5270	1			T4	6		T8	4		T15	12
valid_sources[0x49]	8288	1			T4	6		T5	2		T16	11
valid_sources[0x4a]	5615	1			T4	5		T5	1		T7	1
valid_sources[0x4b]	5522	1			T4	2		T5	2		T11	2
valid_sources[0x4c]	6269	1			T4	3		T11	4		T7	3
valid_sources[0x4d]	6304	1			T4	5		T5	2		T8	2
valid_sources[0x4e]	5413	1			T4	3		T5	1		T7	5
valid_sources[0x4f]	6374	1			T4	1		T8	3		T15	1
valid_sources[0x50]	5624	1			T4	1		T5	3		T7	2
valid_sources[0x51]	5540	1			T4	7		T5	2		T11	1
valid_sources[0x52]	10146	1			T4	3		T5	1		T7	2
valid_sources[0x53]	5647	1			T4	1		T5	1		T15	9
valid_sources[0x54]	5838	1			T4	3		T5	4		T11	7
valid_sources[0x55]	5856	1			T4	6		T5	1		T11	4
valid_sources[0x56]	9251	1			T4	5		T5	1		T11	5
valid_sources[0x57]	6353	1			T4	3		T5	3		T11	4
valid_sources[0x58]	5531	1			T4	5		T5	2		T8	2
valid_sources[0x59]	7107	1			T4	2		T5	1		T7	3
valid_sources[0x5a]	5824	1			T4	3		T5	1		T11	1
valid_sources[0x5b]	5527	1			T5	3		T7	4		T15	5
valid_sources[0x5c]	5940	1			T4	5		T9	3		T16	7
valid_sources[0x5d]	8144	1			T4	5		T5	4		T7	1
valid_sources[0x5e]	5801	1			T4	3		T8	1		T14	17
valid_sources[0x5f]	11874	1			T4	2		T8	1		T15	1
valid_sources[0x60]	5835	1			T4	2		T5	3		T11	5
valid_sources[0x61]	10612	1			T4	2		T5	1		T11	4
valid_sources[0x62]	5624	1			T4	4		T5	6		T7	7
valid_sources[0x63]	5644	1			T4	6		T5	1		T11	2
valid_sources[0x64]	4874	1			T4	1		T5	1		T11	1
valid_sources[0x65]	6556	1			T4	2		T5	3		T8	2
valid_sources[0x66]	5211	1			T4	4		T5	2		T15	47
valid_sources[0x67]	6136	1			T4	7		T5	1		T11	2
valid_sources[0x68]	6840	1			T4	4		T11	1		T7	6
valid_sources[0x69]	7557	1			T4	3		T5	3		T7	5
valid_sources[0x6a]	5936	1			T4	6		T5	3		T8	1
valid_sources[0x6b]	5504	1			T4	1		T5	2		T7	1
valid_sources[0x6c]	9032	1			T4	3		T5	2		T11	16
valid_sources[0x6d]	5868	1			T4	1		T11	12		T8	1
valid_sources[0x6e]	10743	1			T4	1		T5	1		T7	1
valid_sources[0x6f]	6341	1			T4	11		T5	1		T8	1
valid_sources[0x70]	5710	1			T4	6		T8	2		T14	16
valid_sources[0x71]	8006	1			T4	1		T5	5		T8	2
valid_sources[0x72]	5715	1			T4	2		T5	2		T7	3
valid_sources[0x73]	7005	1			T6	5		T4	1		T5	1
valid_sources[0x74]	5716	1			T4	6		T5	1		T7	1
valid_sources[0x75]	6031	1			T4	1		T5	1		T11	5
valid_sources[0x76]	10431	1			T4	3		T5	2		T11	4
valid_sources[0x77]	7226	1			T4	1		T5	6		T7	2
valid_sources[0x78]	5735	1			T4	2		T5	3		T7	1
valid_sources[0x79]	6639	1			T4	4		T5	3		T7	1
valid_sources[0x7a]	5137	1			T4	1		T5	1		T11	5
valid_sources[0x7b]	5798	1			T4	2		T5	2		T7	7
valid_sources[0x7c]	5603	1			T4	2		T5	2		T11	9
valid_sources[0x7d]	5043	1			T4	1		T5	2		T14	9
valid_sources[0x7e]	5511	1			T4	1		T7	1		T8	1
valid_sources[0x7f]	6414	1			T4	2		T5	1		T14	2
valid_sources[0x80]	6009	1			T4	3		T5	2		T11	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

792890

1

T1

6

T2

155

T3

1126

values[0x0]

all_enables

biggest_size

129066

1

T1

1

T2

48

T3

288

values[0x1]

all_enables

biggest_size

127943

1

T1

6

T2

26

T3

327