Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	61168070	14885	0	0
claim_transition_if_regwen_rd_A	61168070	1554	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61168070	14885	0	0
T7	33224	0	0	0
T8	36351	0	0	0
T9	39660	0	0	0
T10	385306	19	0	0
T14	47124	0	0	0
T15	36848	0	0	0
T16	34356	0	0	0
T17	68440	0	0	0
T25	8510	0	0	0
T26	30777	0	0	0
T36	0	6	0	0
T37	0	4	0	0
T91	0	1	0	0
T92	0	7	0	0
T154	0	2	0	0
T155	0	17	0	0
T156	0	3	0	0
T157	0	2	0	0
T158	0	2	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61168070	1554	0	0
T21	111666	0	0	0
T35	57456	0	0	0
T37	389667	16	0	0
T62	1134	0	0	0
T90	567108	0	0	0
T91	131796	0	0	0
T101	12470	0	0	0
T120	0	39	0	0
T122	0	90	0	0
T157	0	7	0	0
T159	0	7	0	0
T160	0	4	0	0
T161	0	2	0	0
T162	0	3	0	0
T163	0	1	0	0
T164	0	6	0	0
T165	27838	0	0	0
T166	68423	0	0	0
T167	17729	0	0	0