Design subhierarchy
dashboard | hierarchy | modlist | groups | tests | asserts

Go up
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
 gen_syncs[0].u_prim_lc_sync_flash_rma_ack 100.00 100.00 100.00 100.00
 gen_syncs[1].u_prim_lc_sync_flash_rma_ack 100.00 100.00 100.00 100.00
 u_cnt_regs 100.00 100.00 100.00 100.00
 u_fsm_state_regs 100.00 100.00 100.00 100.00
u_lc_ctrl_fsm_cov_if 96.97 100.00 90.91 100.00
 u_lc_ctrl_signal_decode 98.86 99.21 97.37 100.00
 u_lc_ctrl_state_decode 98.89 100.00 100.00 96.67
u_lc_ctrl_state_transition 89.97 98.48 75.00 96.43
 u_prim_lc_sender_check_byp_en 100.00 100.00 100.00
 u_prim_lc_sender_clk_byp_req 100.00 100.00 100.00
 u_prim_lc_sender_flash_rma_req 100.00 100.00 100.00
 u_prim_lc_sync_clk_byp_ack 100.00 100.00 100.00 100.00
 u_prim_lc_sync_flash_rma_ack_buf 100.00 100.00 100.00
 u_prim_lc_sync_rma_token_valid 100.00 100.00 100.00
 u_prim_lc_sync_test_token_valid 100.00 100.00 100.00
 u_state_regs 100.00 100.00 100.00 100.00