Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	56444155	13776	0	0
claim_transition_if_regwen_rd_A	56444155	1369	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56444155	13776	0	0
T66	21749	0	0	0
T101	228703	2	0	0
T102	0	3	0	0
T103	0	17	0	0
T149	0	4	0	0
T150	0	9	0	0
T151	0	4	0	0
T152	0	4	0	0
T153	0	3	0	0
T154	0	1	0	0
T155	0	12	0	0
T156	2165	0	0	0
T157	1543	0	0	0
T158	3030	0	0	0
T159	226515	0	0	0
T160	1290	0	0	0
T161	34170	0	0	0
T162	66571	0	0	0
T163	25992	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56444155	1369	0	0
T102	470432	4	0	0
T110	0	4	0	0
T111	0	19	0	0
T145	0	111	0	0
T149	0	4	0	0
T153	0	4	0	0
T164	0	7	0	0
T165	0	6	0	0
T166	0	5	0	0
T167	0	7	0	0
T168	962	0	0	0
T169	1154	0	0	0
T170	152791	0	0	0
T171	2941	0	0	0
T172	34792	0	0	0
T173	36317	0	0	0
T174	56036	0	0	0
T175	34906	0	0	0
T176	6619	0	0	0