Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	813159	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

994850

1

T1

15

T2

1987

T3

288

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1524596	1			T1	35		T2	3837		T3	209
values[0x0]	141313	1			T1	8		T2	68		T3	99
values[0x1]	142100	1			T1	8		T2	68		T3	109

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	643636	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1164373

1

T1

31

T2

2382

T3

323

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5560	1			T2	23		T12	3		T13	2
valid_sources[0x01]	5488	1			T2	13		T4	1		T12	3
valid_sources[0x02]	5264	1			T2	9		T12	5		T13	4
valid_sources[0x03]	5261	1			T2	17		T12	1		T13	1
valid_sources[0x04]	5762	1			T2	11		T4	5		T13	4
valid_sources[0x05]	7425	1			T2	18		T12	4		T13	3
valid_sources[0x06]	5476	1			T2	20		T4	1		T13	6
valid_sources[0x07]	5654	1			T2	11		T4	1		T12	3
valid_sources[0x08]	5261	1			T2	12		T12	5		T13	8
valid_sources[0x09]	5407	1			T2	14		T12	2		T13	5
valid_sources[0x0a]	5245	1			T2	20		T4	9		T12	5
valid_sources[0x0b]	5332	1			T2	15		T12	8		T13	6
valid_sources[0x0c]	5689	1			T2	10		T12	2		T13	1
valid_sources[0x0d]	7419	1			T1	1		T2	16		T12	3
valid_sources[0x0e]	10985	1			T1	4		T2	15		T4	1
valid_sources[0x0f]	5366	1			T2	13		T4	1		T12	7
valid_sources[0x10]	30161	1			T2	10		T12	4		T13	1
valid_sources[0x11]	5432	1			T2	12		T12	1		T13	3
valid_sources[0x12]	8992	1			T2	17		T12	3		T13	3
valid_sources[0x13]	5372	1			T2	5		T12	3		T13	8
valid_sources[0x14]	5654	1			T2	16		T4	2		T12	2
valid_sources[0x15]	6530	1			T2	18		T13	2		T15	9
valid_sources[0x16]	5621	1			T2	13		T4	2		T12	1
valid_sources[0x17]	5426	1			T2	14		T12	1		T13	5
valid_sources[0x18]	6456	1			T2	11		T13	5		T15	14
valid_sources[0x19]	5346	1			T2	11		T12	4		T13	7
valid_sources[0x1a]	5124	1			T2	11		T4	1		T12	3
valid_sources[0x1b]	6626	1			T2	13		T12	1		T13	6
valid_sources[0x1c]	5861	1			T2	16		T4	2		T12	6
valid_sources[0x1d]	13561	1			T2	15		T12	1		T13	4
valid_sources[0x1e]	6858	1			T2	25		T12	5		T13	2
valid_sources[0x1f]	7632	1			T2	19		T12	3		T13	5
valid_sources[0x20]	5331	1			T2	19		T12	4		T13	6
valid_sources[0x21]	5483	1			T2	17		T13	3		T15	8
valid_sources[0x22]	6076	1			T2	17		T12	1		T13	6
valid_sources[0x23]	6381	1			T2	20		T4	6		T13	7
valid_sources[0x24]	5428	1			T2	17		T12	10		T13	8
valid_sources[0x25]	7513	1			T2	9		T12	2		T13	5
valid_sources[0x26]	5350	1			T2	21		T12	2		T13	3
valid_sources[0x27]	5662	1			T2	8		T12	3		T13	5
valid_sources[0x28]	5926	1			T2	18		T12	1		T13	8
valid_sources[0x29]	5188	1			T1	3		T2	17		T12	1
valid_sources[0x2a]	6745	1			T2	25		T13	6		T15	6
valid_sources[0x2b]	5585	1			T2	10		T12	3		T13	4
valid_sources[0x2c]	5498	1			T2	8		T4	4		T12	1
valid_sources[0x2d]	5479	1			T2	10		T4	1		T12	6
valid_sources[0x2e]	5326	1			T2	12		T12	2		T15	8
valid_sources[0x2f]	5310	1			T2	27		T13	7		T15	2
valid_sources[0x30]	5468	1			T2	10		T12	3		T13	1
valid_sources[0x31]	5369	1			T2	14		T12	2		T13	4
valid_sources[0x32]	5378	1			T2	12		T12	5		T13	3
valid_sources[0x33]	8421	1			T2	8		T12	13		T13	12
valid_sources[0x34]	10489	1			T2	17		T12	2		T13	8
valid_sources[0x35]	6320	1			T2	13		T12	5		T13	1
valid_sources[0x36]	5630	1			T2	19		T12	4		T13	9
valid_sources[0x37]	5525	1			T2	18		T12	10		T13	5
valid_sources[0x38]	5411	1			T2	18		T4	2		T12	3
valid_sources[0x39]	7843	1			T2	12		T12	8		T13	1
valid_sources[0x3a]	5376	1			T1	2		T2	16		T4	5
valid_sources[0x3b]	6933	1			T2	13		T4	1		T12	5
valid_sources[0x3c]	5242	1			T2	13		T12	4		T13	2
valid_sources[0x3d]	7626	1			T2	11		T12	2		T13	4
valid_sources[0x3e]	5351	1			T2	20		T12	6		T13	3
valid_sources[0x3f]	7148	1			T1	3		T2	19		T12	3
valid_sources[0x40]	7230	1			T2	17		T12	3		T13	2
valid_sources[0x41]	5494	1			T2	17		T12	5		T13	4
valid_sources[0x42]	5202	1			T2	6		T12	11		T13	7
valid_sources[0x43]	5290	1			T2	22		T12	3		T15	5
valid_sources[0x44]	5501	1			T2	11		T12	7		T13	2
valid_sources[0x45]	5381	1			T2	17		T4	1		T13	4
valid_sources[0x46]	5266	1			T2	12		T4	1		T12	7
valid_sources[0x47]	6389	1			T2	14		T4	3		T13	3
valid_sources[0x48]	5499	1			T2	27		T12	6		T13	5
valid_sources[0x49]	5541	1			T2	9		T12	2		T13	3
valid_sources[0x4a]	5277	1			T2	23		T4	2		T12	3
valid_sources[0x4b]	5238	1			T2	15		T12	1		T16	15
valid_sources[0x4c]	5506	1			T2	13		T12	6		T13	6
valid_sources[0x4d]	6321	1			T2	24		T12	7		T13	3
valid_sources[0x4e]	5664	1			T2	8		T4	1		T12	3
valid_sources[0x4f]	5307	1			T2	12		T12	3		T13	1
valid_sources[0x50]	5585	1			T2	11		T4	1		T12	3
valid_sources[0x51]	9655	1			T2	16		T12	3		T13	3
valid_sources[0x52]	5256	1			T2	17		T12	5		T13	2
valid_sources[0x53]	5275	1			T2	10		T4	2		T12	3
valid_sources[0x54]	5261	1			T2	21		T12	3		T13	2
valid_sources[0x55]	6194	1			T2	17		T12	3		T13	8
valid_sources[0x56]	9818	1			T2	17		T12	1		T13	7
valid_sources[0x57]	6891	1			T2	13		T4	5		T12	4
valid_sources[0x58]	5699	1			T1	4		T2	16		T12	4
valid_sources[0x59]	5431	1			T2	20		T12	7		T13	3
valid_sources[0x5a]	6284	1			T2	11		T12	2		T13	9
valid_sources[0x5b]	5439	1			T2	26		T12	3		T13	6
valid_sources[0x5c]	5440	1			T2	25		T12	2		T13	7
valid_sources[0x5d]	5409	1			T2	25		T13	6		T15	15
valid_sources[0x5e]	6427	1			T2	12		T12	1		T13	11
valid_sources[0x5f]	7189	1			T2	12		T4	2		T12	4
valid_sources[0x60]	5661	1			T2	14		T12	1		T13	5
valid_sources[0x61]	5823	1			T2	21		T12	2		T13	4
valid_sources[0x62]	9715	1			T2	16		T4	3		T12	2
valid_sources[0x63]	5428	1			T2	17		T12	5		T13	6
valid_sources[0x64]	6215	1			T2	15		T12	1		T13	4
valid_sources[0x65]	5403	1			T2	16		T4	4		T12	1
valid_sources[0x66]	6237	1			T2	9		T12	1		T13	5
valid_sources[0x67]	5356	1			T2	17		T4	1		T12	6
valid_sources[0x68]	6503	1			T2	17		T4	3		T12	2
valid_sources[0x69]	5116	1			T2	20		T12	4		T13	6
valid_sources[0x6a]	6832	1			T2	22		T12	1		T13	6
valid_sources[0x6b]	5318	1			T1	2		T2	12		T12	3
valid_sources[0x6c]	5675	1			T2	20		T4	2		T12	2
valid_sources[0x6d]	5266	1			T2	10		T12	4		T13	2
valid_sources[0x6e]	5654	1			T2	10		T12	4		T13	10
valid_sources[0x6f]	5565	1			T1	1		T2	13		T12	3
valid_sources[0x70]	5461	1			T2	16		T12	3		T13	6
valid_sources[0x71]	6327	1			T2	23		T4	1		T13	2
valid_sources[0x72]	5393	1			T2	13		T12	1		T13	4
valid_sources[0x73]	5420	1			T2	14		T12	7		T13	7
valid_sources[0x74]	5509	1			T2	22		T12	16		T15	14
valid_sources[0x75]	5270	1			T2	18		T13	3		T15	8
valid_sources[0x76]	6142	1			T2	16		T12	3		T13	7
valid_sources[0x77]	5337	1			T2	11		T12	2		T13	4
valid_sources[0x78]	5620	1			T2	11		T12	1		T13	7
valid_sources[0x79]	137973	1			T2	14		T12	5		T13	4
valid_sources[0x7a]	5445	1			T2	12		T12	2		T13	6
valid_sources[0x7b]	30240	1			T1	1		T2	12		T12	4
valid_sources[0x7c]	6024	1			T2	12		T12	4		T13	4
valid_sources[0x7d]	6889	1			T2	14		T13	3		T14	3
valid_sources[0x7e]	44509	1			T2	16		T12	4		T13	5
valid_sources[0x7f]	5713	1			T2	29		T4	1		T12	1
valid_sources[0x80]	5609	1			T2	18		T4	2		T12	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

750903

1

T1

1

T2

1874

T3

106

values[0x0]

all_enables

biggest_size

122405

1

T1

7

T2

57

T3

84

values[0x1]

all_enables

biggest_size

121542

1

T1

7

T2

56

T3

98