Unified Coverage Report :: Module :: prim_sec_anchor_buf

Module : prim_sec_anchor_buf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_prim_sec_anchor_0.1/rtl/prim_sec_anchor_buf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[0].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[1].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[2].u_prim_buf
tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[1].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[1].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[1].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[1].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[2].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[2].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[2].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[2].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[3].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[3].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[3].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[3].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[1].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[1].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[1].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[1].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[2].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[2].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[2].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[2].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[1].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[1].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[1].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[1].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[2].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[2].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[2].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[2].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[3].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[3].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[3].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[3].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[1].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[1].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[1].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[1].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[2].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[2].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[2].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[2].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[3].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[3].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[3].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[3].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[4].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[4].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[4].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[4].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[5].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[5].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[5].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[5].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[6].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[6].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[6].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[6].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[7].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[7].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[7].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[7].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_decode.u_prim_sec_anchor_buf
tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.gen_buffs[0].gen_bits[3].u_prim_buf

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_prim_lc_sync.gen_buffs[1].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_clk_byp_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_clk_byp_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_clk_byp_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_clk_byp_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[1].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_clk_byp_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[1].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_clk_byp_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[1].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_clk_byp_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[1].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_clk_byp_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[2].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_clk_byp_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[2].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_clk_byp_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[2].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_clk_byp_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[2].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_clk_byp_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[3].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_clk_byp_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[3].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_clk_byp_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[3].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_clk_byp_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_clk_byp_ack.gen_buffs[3].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_clk_byp_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_flash_rma_ack_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_flash_rma_ack_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_flash_rma_ack_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_flash_rma_ack_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[1].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_flash_rma_ack_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[1].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_flash_rma_ack_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[1].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_flash_rma_ack_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[1].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_flash_rma_ack_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[2].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_flash_rma_ack_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[2].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_flash_rma_ack_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[2].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_flash_rma_ack_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_flash_rma_ack_buf.gen_buffs[2].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_flash_rma_ack_buf

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_rma_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_rma_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_rma_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_rma_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[1].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_rma_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[1].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_rma_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[1].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_rma_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[1].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_rma_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[2].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_rma_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[2].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_rma_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[2].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_rma_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[2].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_rma_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[3].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_rma_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[3].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_rma_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[3].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_rma_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_rma_token_valid.gen_buffs[3].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_rma_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[1].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[1].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[1].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[1].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[2].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[2].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[2].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[2].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[3].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[3].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[3].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[3].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[4].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[4].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[4].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[4].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[5].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[5].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[5].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[5].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[6].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[6].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[6].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[6].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[7].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[7].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[7].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_prim_lc_sync_test_token_valid.gen_buffs[7].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_prim_lc_sync_test_token_valid

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_state_decode.u_prim_sec_anchor_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.89	100.00	100.00			96.67		u_lc_ctrl_state_decode

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_syncs[0].u_prim_lc_sync_flash_rma_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_syncs[0].u_prim_lc_sync_flash_rma_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_syncs[0].u_prim_lc_sync_flash_rma_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[0].u_prim_lc_sync_flash_rma_ack.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_syncs[0].u_prim_lc_sync_flash_rma_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_syncs[1].u_prim_lc_sync_flash_rma_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_syncs[1].u_prim_lc_sync_flash_rma_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_syncs[1].u_prim_lc_sync_flash_rma_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.gen_syncs[1].u_prim_lc_sync_flash_rma_ack.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	gen_syncs[1].u_prim_lc_sync_flash_rma_ack

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	100.00	100.00