Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	62513957	15119	0	0
claim_transition_if_regwen_rd_A	62513957	1040	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62513957	15119	0	0
T27	28620	0	0	0
T68	19071	0	0	0
T69	40605	0	0	0
T79	19640	0	0	0
T99	249113	2	0	0
T100	0	3	0	0
T101	0	4	0	0
T139	0	3	0	0
T140	0	6	0	0
T141	0	1	0	0
T142	0	8	0	0
T143	0	7	0	0
T144	0	6	0	0
T145	0	2	0	0
T146	856	0	0	0
T147	33718	0	0	0
T148	24554	0	0	0
T149	398750	0	0	0
T150	44099	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62513957	1040	0	0
T27	28620	0	0	0
T68	19071	0	0	0
T69	40605	0	0	0
T79	19640	0	0	0
T99	249113	1	0	0
T110	0	33	0	0
T115	0	17	0	0
T136	0	2	0	0
T140	0	6	0	0
T145	0	3	0	0
T146	856	0	0	0
T147	33718	0	0	0
T148	24554	0	0	0
T149	398750	0	0	0
T150	44099	0	0	0
T151	0	11	0	0
T152	0	3	0	0
T153	0	57	0	0
T154	0	5	0	0