Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	766687	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

958020

1

T1

12

T3

153

T4

200

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1427061	1			T1	38		T2	2		T3	116
values[0x0]	148457	1			T1	9		T3	65		T4	49
values[0x1]	149189	1			T1	7		T2	1		T3	56

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	606377	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1118330

1

T1

24

T3

174

T4

217

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5359	1			T4	3		T11	4		T22	1
valid_sources[0x01]	5648	1			T11	6		T14	6		T35	5
valid_sources[0x02]	5174	1			T1	1		T11	5		T13	1
valid_sources[0x03]	7747	1			T4	2		T11	8		T22	1
valid_sources[0x04]	8186	1			T4	2		T11	4		T22	1
valid_sources[0x05]	5635	1			T11	6		T22	1		T13	1
valid_sources[0x06]	5111	1			T4	1		T11	4		T22	1
valid_sources[0x07]	4961	1			T4	3		T11	5		T13	3
valid_sources[0x08]	5333	1			T4	1		T11	3		T37	13
valid_sources[0x09]	5548	1			T4	1		T11	8		T14	1
valid_sources[0x0a]	6148	1			T11	5		T13	4		T14	3
valid_sources[0x0b]	5153	1			T4	1		T11	8		T13	1
valid_sources[0x0c]	5331	1			T1	1		T11	4		T22	1
valid_sources[0x0d]	6339	1			T4	2		T11	10		T22	1
valid_sources[0x0e]	5535	1			T4	1		T11	4		T13	2
valid_sources[0x0f]	5623	1			T11	10		T22	1		T14	8
valid_sources[0x10]	8840	1			T4	2		T11	8		T13	1
valid_sources[0x11]	5142	1			T4	1		T11	7		T22	1
valid_sources[0x12]	13733	1			T4	1		T11	11		T13	1
valid_sources[0x13]	6304	1			T1	1		T11	9		T22	1
valid_sources[0x14]	6125	1			T1	1		T11	4		T13	4
valid_sources[0x15]	5635	1			T1	1		T11	10		T22	1
valid_sources[0x16]	5314	1			T4	2		T11	5		T14	2
valid_sources[0x17]	9354	1			T4	1		T11	9		T14	7
valid_sources[0x18]	6447	1			T11	3		T22	2		T13	1
valid_sources[0x19]	5512	1			T4	3		T11	8		T13	3
valid_sources[0x1a]	5169	1			T4	2		T11	5		T14	8
valid_sources[0x1b]	5250	1			T4	2		T11	2		T13	3
valid_sources[0x1c]	6096	1			T4	4		T11	8		T14	2
valid_sources[0x1d]	5616	1			T1	2		T4	3		T11	7
valid_sources[0x1e]	5469	1			T1	1		T11	7		T22	1
valid_sources[0x1f]	6319	1			T11	4		T22	1		T14	13
valid_sources[0x20]	5938	1			T1	1		T4	3		T11	15
valid_sources[0x21]	5544	1			T1	1		T11	8		T13	6
valid_sources[0x22]	6336	1			T4	1		T11	8		T22	1
valid_sources[0x23]	5430	1			T4	3		T11	6		T13	2
valid_sources[0x24]	6871	1			T11	13		T14	1		T17	2
valid_sources[0x25]	7289	1			T4	1		T11	8		T13	1
valid_sources[0x26]	5078	1			T1	1		T4	1		T11	10
valid_sources[0x27]	5262	1			T4	1		T11	3		T22	1
valid_sources[0x28]	5179	1			T4	2		T11	11		T13	1
valid_sources[0x29]	5345	1			T11	8		T22	1		T13	2
valid_sources[0x2a]	5338	1			T4	1		T11	10		T22	1
valid_sources[0x2b]	5733	1			T11	7		T13	2		T14	1
valid_sources[0x2c]	6179	1			T11	6		T22	1		T14	1
valid_sources[0x2d]	5412	1			T1	1		T4	1		T11	6
valid_sources[0x2e]	7882	1			T11	9		T13	6		T14	1
valid_sources[0x2f]	5543	1			T1	1		T4	2		T11	3
valid_sources[0x30]	6479	1			T1	1		T11	5		T13	3
valid_sources[0x31]	5510	1			T1	1		T11	13		T13	3
valid_sources[0x32]	5431	1			T4	3		T11	9		T13	3
valid_sources[0x33]	5499	1			T1	1		T4	1		T11	14
valid_sources[0x34]	5854	1			T1	1		T11	7		T13	1
valid_sources[0x35]	7147	1			T11	7		T14	1		T16	2
valid_sources[0x36]	5340	1			T11	3		T13	1		T14	7
valid_sources[0x37]	8165	1			T4	3		T11	10		T13	1
valid_sources[0x38]	5276	1			T4	1		T11	4		T13	6
valid_sources[0x39]	5329	1			T4	1		T11	7		T22	1
valid_sources[0x3a]	6630	1			T1	1		T4	2		T11	4
valid_sources[0x3b]	5284	1			T11	8		T13	5		T14	1
valid_sources[0x3c]	5391	1			T11	3		T22	2		T14	2
valid_sources[0x3d]	5646	1			T4	1		T11	11		T13	2
valid_sources[0x3e]	7006	1			T4	1		T11	6		T13	1
valid_sources[0x3f]	7910	1			T4	1		T11	9		T13	2
valid_sources[0x40]	5187	1			T4	2		T6	21		T11	9
valid_sources[0x41]	5266	1			T4	2		T11	3		T22	1
valid_sources[0x42]	17988	1			T4	2		T11	11		T13	2
valid_sources[0x43]	6752	1			T1	1		T11	9		T13	1
valid_sources[0x44]	5422	1			T4	2		T11	5		T13	2
valid_sources[0x45]	5251	1			T1	1		T4	2		T11	7
valid_sources[0x46]	7812	1			T11	12		T14	1		T37	3
valid_sources[0x47]	5342	1			T4	2		T11	7		T13	5
valid_sources[0x48]	5602	1			T4	1		T11	9		T14	3
valid_sources[0x49]	5583	1			T4	2		T11	10		T13	2
valid_sources[0x4a]	5570	1			T4	3		T11	7		T97	1
valid_sources[0x4b]	5582	1			T1	1		T4	5		T11	11
valid_sources[0x4c]	5681	1			T4	2		T11	10		T22	1
valid_sources[0x4d]	13950	1			T4	2		T11	13		T14	7
valid_sources[0x4e]	5443	1			T4	2		T11	8		T13	6
valid_sources[0x4f]	5423	1			T4	1		T11	8		T13	4
valid_sources[0x50]	6647	1			T4	1		T11	7		T22	1
valid_sources[0x51]	5195	1			T4	1		T6	13		T11	11
valid_sources[0x52]	9956	1			T11	8		T14	5		T16	2
valid_sources[0x53]	5401	1			T1	1		T4	2		T11	3
valid_sources[0x54]	5610	1			T1	1		T4	1		T11	10
valid_sources[0x55]	5442	1			T11	4		T13	3		T14	1
valid_sources[0x56]	6404	1			T1	1		T4	1		T11	6
valid_sources[0x57]	5390	1			T4	1		T11	12		T13	5
valid_sources[0x58]	5732	1			T4	1		T11	4		T14	1
valid_sources[0x59]	7977	1			T4	2		T11	5		T13	1
valid_sources[0x5a]	5456	1			T11	9		T13	2		T14	2
valid_sources[0x5b]	5541	1			T11	7		T13	1		T14	1
valid_sources[0x5c]	5693	1			T4	2		T11	8		T13	1
valid_sources[0x5d]	5304	1			T11	12		T14	5		T35	4
valid_sources[0x5e]	7522	1			T11	7		T13	1		T14	7
valid_sources[0x5f]	5431	1			T4	1		T11	10		T14	1
valid_sources[0x60]	6188	1			T4	1		T11	6		T22	1
valid_sources[0x61]	47563	1			T1	1		T11	11		T22	1
valid_sources[0x62]	5212	1			T11	4		T13	1		T14	3
valid_sources[0x63]	5883	1			T4	2		T11	9		T22	1
valid_sources[0x64]	7489	1			T4	2		T11	6		T13	1
valid_sources[0x65]	5696	1			T4	2		T11	7		T22	1
valid_sources[0x66]	5506	1			T4	2		T11	9		T22	1
valid_sources[0x67]	5244	1			T4	1		T11	3		T22	1
valid_sources[0x68]	5741	1			T4	1		T11	11		T16	5
valid_sources[0x69]	7145	1			T11	5		T22	1		T14	5
valid_sources[0x6a]	5259	1			T4	1		T11	7		T13	1
valid_sources[0x6b]	5425	1			T11	7		T13	1		T14	3
valid_sources[0x6c]	5161	1			T1	1		T4	1		T11	7
valid_sources[0x6d]	7981	1			T4	1		T11	6		T13	2
valid_sources[0x6e]	5280	1			T4	2		T11	14		T22	1
valid_sources[0x6f]	22242	1			T4	1		T11	14		T14	7
valid_sources[0x70]	10962	1			T4	3		T11	8		T13	5
valid_sources[0x71]	16901	1			T1	1		T11	12		T13	3
valid_sources[0x72]	6482	1			T4	4		T11	7		T7	122
valid_sources[0x73]	5353	1			T4	1		T11	8		T14	3
valid_sources[0x74]	6650	1			T4	1		T11	8		T13	1
valid_sources[0x75]	5342	1			T4	1		T11	12		T13	2
valid_sources[0x76]	5493	1			T4	1		T11	7		T13	4
valid_sources[0x77]	5682	1			T4	4		T11	5		T22	1
valid_sources[0x78]	5262	1			T2	3		T11	12		T13	4
valid_sources[0x79]	5457	1			T1	1		T4	1		T14	5
valid_sources[0x7a]	7943	1			T11	7		T13	1		T14	12
valid_sources[0x7b]	5203	1			T11	6		T13	1		T14	7
valid_sources[0x7c]	6314	1			T11	7		T13	3		T14	2
valid_sources[0x7d]	5534	1			T11	5		T13	1		T14	5
valid_sources[0x7e]	5623	1			T1	1		T4	3		T11	8
valid_sources[0x7f]	5411	1			T11	8		T7	1		T12	6
valid_sources[0x80]	5286	1			T4	2		T11	6		T22	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

701715

1

T1

1

T3

44

T4

114

values[0x0]

all_enables

biggest_size

128683

1

T1

6

T3

59

T4

43

values[0x1]

all_enables

biggest_size

127622

1

T1

5

T3

50

T4

43