Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	56723035	14101	0	0
claim_transition_if_regwen_rd_A	56723035	2344	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56723035	14101	0	0
T50	129625	2	0	0
T57	31111	0	0	0
T101	0	2	0	0
T102	0	7	0	0
T114	0	3	0	0
T118	0	5	0	0
T153	0	3	0	0
T154	0	3	0	0
T155	0	12	0	0
T156	0	3	0	0
T157	0	17	0	0
T158	954	0	0	0
T159	1835	0	0	0
T160	61492	0	0	0
T161	6041	0	0	0
T162	21038	0	0	0
T163	7727	0	0	0
T164	107584	0	0	0
T165	55181	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56723035	2344	0	0
T50	129625	4	0	0
T57	31111	0	0	0
T116	0	41	0	0
T120	0	10	0	0
T154	0	11	0	0
T158	954	0	0	0
T159	1835	0	0	0
T160	61492	0	0	0
T161	6041	0	0	0
T162	21038	0	0	0
T163	7727	0	0	0
T164	107584	0	0	0
T165	55181	0	0	0
T166	0	2	0	0
T167	0	16	0	0
T168	0	7	0	0
T169	0	7	0	0
T170	0	56	0	0
T171	0	265	0	0