| T358 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.3615207774 |
|
|
Aug 25 10:33:55 AM UTC 24 |
Aug 25 10:33:58 AM UTC 24 |
85716854 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.3025795765 |
|
|
Aug 25 10:33:48 AM UTC 24 |
Aug 25 10:33:59 AM UTC 24 |
690140524 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.3292865425 |
|
|
Aug 25 10:33:42 AM UTC 24 |
Aug 25 10:34:00 AM UTC 24 |
354810293 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2705975571 |
|
|
Aug 25 10:33:59 AM UTC 24 |
Aug 25 10:34:01 AM UTC 24 |
15012047 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_errors.1376982674 |
|
|
Aug 25 10:33:42 AM UTC 24 |
Aug 25 10:34:02 AM UTC 24 |
1129140195 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_access.2547817063 |
|
|
Aug 25 10:33:49 AM UTC 24 |
Aug 25 10:34:06 AM UTC 24 |
3222226712 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_errors.120467535 |
|
|
Aug 25 10:32:49 AM UTC 24 |
Aug 25 10:34:06 AM UTC 24 |
5022183752 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.3568691688 |
|
|
Aug 25 10:33:52 AM UTC 24 |
Aug 25 10:34:07 AM UTC 24 |
240989152 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.1037288970 |
|
|
Aug 25 10:34:01 AM UTC 24 |
Aug 25 10:34:08 AM UTC 24 |
186368906 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.266858628 |
|
|
Aug 25 10:33:59 AM UTC 24 |
Aug 25 10:34:09 AM UTC 24 |
150974281 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.67615076 |
|
|
Aug 25 10:33:51 AM UTC 24 |
Aug 25 10:34:11 AM UTC 24 |
498535910 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.1449990659 |
|
|
Aug 25 10:34:08 AM UTC 24 |
Aug 25 10:34:14 AM UTC 24 |
338656323 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.3433243126 |
|
|
Aug 25 10:33:48 AM UTC 24 |
Aug 25 10:34:15 AM UTC 24 |
2748892192 ps |
| T85 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.2308866259 |
|
|
Aug 25 10:34:06 AM UTC 24 |
Aug 25 10:34:15 AM UTC 24 |
950315933 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.3908343661 |
|
|
Aug 25 10:34:00 AM UTC 24 |
Aug 25 10:34:16 AM UTC 24 |
169801724 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_access.1099057365 |
|
|
Aug 25 10:33:31 AM UTC 24 |
Aug 25 10:34:18 AM UTC 24 |
2877563497 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.2521332586 |
|
|
Aug 25 10:33:29 AM UTC 24 |
Aug 25 10:34:19 AM UTC 24 |
1351163649 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.2398624668 |
|
|
Aug 25 10:34:09 AM UTC 24 |
Aug 25 10:34:19 AM UTC 24 |
184335500 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.3879568054 |
|
|
Aug 25 10:33:54 AM UTC 24 |
Aug 25 10:34:19 AM UTC 24 |
2741957603 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.4218330144 |
|
|
Aug 25 10:32:46 AM UTC 24 |
Aug 25 10:34:19 AM UTC 24 |
1930259166 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.2958137241 |
|
|
Aug 25 10:34:17 AM UTC 24 |
Aug 25 10:34:19 AM UTC 24 |
43688609 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_errors.3601817024 |
|
|
Aug 25 10:34:02 AM UTC 24 |
Aug 25 10:34:21 AM UTC 24 |
570474975 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.2443088963 |
|
|
Aug 25 10:34:03 AM UTC 24 |
Aug 25 10:34:21 AM UTC 24 |
1617465432 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.1550857290 |
|
|
Aug 25 10:34:09 AM UTC 24 |
Aug 25 10:35:06 AM UTC 24 |
2298564295 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.368849112 |
|
|
Aug 25 10:34:20 AM UTC 24 |
Aug 25 10:34:23 AM UTC 24 |
30095245 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.2603607202 |
|
|
Aug 25 10:34:20 AM UTC 24 |
Aug 25 10:34:24 AM UTC 24 |
151514905 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.1652133482 |
|
|
Aug 25 10:33:00 AM UTC 24 |
Aug 25 10:34:24 AM UTC 24 |
1885430598 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.2711490593 |
|
|
Aug 25 10:34:19 AM UTC 24 |
Aug 25 10:34:25 AM UTC 24 |
233524131 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.162609025 |
|
|
Aug 25 10:33:09 AM UTC 24 |
Aug 25 10:34:28 AM UTC 24 |
14730387724 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.1433990741 |
|
|
Aug 25 10:34:23 AM UTC 24 |
Aug 25 10:34:29 AM UTC 24 |
94805435 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_state_failure.978516251 |
|
|
Aug 25 10:33:21 AM UTC 24 |
Aug 25 10:34:29 AM UTC 24 |
937599110 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.1187562832 |
|
|
Aug 25 10:34:26 AM UTC 24 |
Aug 25 10:34:32 AM UTC 24 |
584280798 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.3359057082 |
|
|
Aug 25 10:34:12 AM UTC 24 |
Aug 25 10:34:33 AM UTC 24 |
1459371996 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.516003047 |
|
|
Aug 25 10:34:14 AM UTC 24 |
Aug 25 10:34:34 AM UTC 24 |
1824039846 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.2491245304 |
|
|
Aug 25 10:34:21 AM UTC 24 |
Aug 25 10:34:34 AM UTC 24 |
812364827 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.2983207969 |
|
|
Aug 25 10:34:20 AM UTC 24 |
Aug 25 10:34:34 AM UTC 24 |
273547894 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.2527237427 |
|
|
Aug 25 10:34:10 AM UTC 24 |
Aug 25 10:34:36 AM UTC 24 |
1207145593 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.4095821480 |
|
|
Aug 25 10:34:35 AM UTC 24 |
Aug 25 10:34:38 AM UTC 24 |
42409281 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.3157766224 |
|
|
Aug 25 10:34:35 AM UTC 24 |
Aug 25 10:34:38 AM UTC 24 |
52791448 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_jtag_state_failure.413252611 |
|
|
Aug 25 10:31:50 AM UTC 24 |
Aug 25 10:34:40 AM UTC 24 |
15494298891 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.1220326544 |
|
|
Aug 25 10:33:12 AM UTC 24 |
Aug 25 10:34:40 AM UTC 24 |
4321031706 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.771831362 |
|
|
Aug 25 10:34:35 AM UTC 24 |
Aug 25 10:34:42 AM UTC 24 |
101823427 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.1737172695 |
|
|
Aug 25 10:34:39 AM UTC 24 |
Aug 25 10:34:42 AM UTC 24 |
17720381 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.1616314385 |
|
|
Aug 25 10:34:25 AM UTC 24 |
Aug 25 10:34:42 AM UTC 24 |
3606525761 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.3072329011 |
|
|
Aug 25 10:33:40 AM UTC 24 |
Aug 25 10:34:45 AM UTC 24 |
1227906430 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.1885438010 |
|
|
Aug 25 10:34:29 AM UTC 24 |
Aug 25 10:34:46 AM UTC 24 |
221835113 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_errors.1274544417 |
|
|
Aug 25 10:34:20 AM UTC 24 |
Aug 25 10:34:47 AM UTC 24 |
1034072226 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.1038396880 |
|
|
Aug 25 10:34:29 AM UTC 24 |
Aug 25 10:34:47 AM UTC 24 |
336070174 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.802441643 |
|
|
Aug 25 10:34:41 AM UTC 24 |
Aug 25 10:34:52 AM UTC 24 |
1600777727 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.1970287119 |
|
|
Aug 25 10:34:37 AM UTC 24 |
Aug 25 10:34:52 AM UTC 24 |
414771947 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.3300994366 |
|
|
Aug 25 10:34:24 AM UTC 24 |
Aug 25 10:34:53 AM UTC 24 |
2632877911 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.793475354 |
|
|
Aug 25 10:34:31 AM UTC 24 |
Aug 25 10:34:54 AM UTC 24 |
607948414 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.463909621 |
|
|
Aug 25 10:33:59 AM UTC 24 |
Aug 25 10:34:54 AM UTC 24 |
637944433 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.90297229 |
|
|
Aug 25 10:33:47 AM UTC 24 |
Aug 25 10:34:54 AM UTC 24 |
5639833909 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.3854527377 |
|
|
Aug 25 10:34:41 AM UTC 24 |
Aug 25 10:34:55 AM UTC 24 |
1561232243 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/6.lc_ctrl_stress_all.1104552985 |
|
|
Aug 25 10:31:38 AM UTC 24 |
Aug 25 10:34:56 AM UTC 24 |
134319158748 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.2132302362 |
|
|
Aug 25 10:34:54 AM UTC 24 |
Aug 25 10:34:57 AM UTC 24 |
93236498 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.2168312384 |
|
|
Aug 25 10:34:56 AM UTC 24 |
Aug 25 10:34:58 AM UTC 24 |
18044534 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.855596463 |
|
|
Aug 25 10:34:08 AM UTC 24 |
Aug 25 10:34:59 AM UTC 24 |
983313740 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.632810290 |
|
|
Aug 25 10:34:43 AM UTC 24 |
Aug 25 10:35:00 AM UTC 24 |
1243872516 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.1911981103 |
|
|
Aug 25 10:34:49 AM UTC 24 |
Aug 25 10:35:00 AM UTC 24 |
447792485 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.2137493862 |
|
|
Aug 25 10:34:56 AM UTC 24 |
Aug 25 10:35:00 AM UTC 24 |
45622412 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.2022163196 |
|
|
Aug 25 10:33:48 AM UTC 24 |
Aug 25 10:35:01 AM UTC 24 |
3368403626 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.2552794269 |
|
|
Aug 25 10:34:48 AM UTC 24 |
Aug 25 10:35:01 AM UTC 24 |
2824356623 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.2342510440 |
|
|
Aug 25 10:34:58 AM UTC 24 |
Aug 25 10:35:04 AM UTC 24 |
93222410 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_errors.1357219714 |
|
|
Aug 25 10:34:39 AM UTC 24 |
Aug 25 10:35:05 AM UTC 24 |
3165298431 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.1221014588 |
|
|
Aug 25 10:34:49 AM UTC 24 |
Aug 25 10:35:06 AM UTC 24 |
952343907 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/5.lc_ctrl_stress_all.3657803877 |
|
|
Aug 25 10:31:12 AM UTC 24 |
Aug 25 10:35:09 AM UTC 24 |
5078933390 ps |
| T421 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.399041580 |
|
|
Aug 25 10:35:00 AM UTC 24 |
Aug 25 10:35:09 AM UTC 24 |
885780789 ps |
| T422 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.2249552327 |
|
|
Aug 25 10:35:05 AM UTC 24 |
Aug 25 10:35:09 AM UTC 24 |
873944745 ps |
| T423 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.3682692034 |
|
|
Aug 25 10:34:57 AM UTC 24 |
Aug 25 10:35:10 AM UTC 24 |
88257800 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.358196960 |
|
|
Aug 25 10:34:20 AM UTC 24 |
Aug 25 10:35:12 AM UTC 24 |
246153739 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.3712581664 |
|
|
Aug 25 10:35:11 AM UTC 24 |
Aug 25 10:35:13 AM UTC 24 |
23243318 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.2794949493 |
|
|
Aug 25 10:34:53 AM UTC 24 |
Aug 25 10:35:14 AM UTC 24 |
726568810 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.3365591307 |
|
|
Aug 25 10:35:13 AM UTC 24 |
Aug 25 10:35:15 AM UTC 24 |
19854583 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.1598014770 |
|
|
Aug 25 10:33:24 AM UTC 24 |
Aug 25 10:35:16 AM UTC 24 |
1585824687 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.2983028950 |
|
|
Aug 25 10:35:16 AM UTC 24 |
Aug 25 10:35:20 AM UTC 24 |
17429529 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.233382949 |
|
|
Aug 25 10:34:59 AM UTC 24 |
Aug 25 10:35:20 AM UTC 24 |
2068261851 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.989352172 |
|
|
Aug 25 10:35:11 AM UTC 24 |
Aug 25 10:35:22 AM UTC 24 |
121814224 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.2639844726 |
|
|
Aug 25 10:35:06 AM UTC 24 |
Aug 25 10:35:22 AM UTC 24 |
435764309 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.3971969006 |
|
|
Aug 25 10:34:43 AM UTC 24 |
Aug 25 10:35:24 AM UTC 24 |
609597884 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.2864525540 |
|
|
Aug 25 10:35:06 AM UTC 24 |
Aug 25 10:35:25 AM UTC 24 |
510745204 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.1564148308 |
|
|
Aug 25 10:35:07 AM UTC 24 |
Aug 25 10:35:25 AM UTC 24 |
1097093628 ps |
| T436 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_errors.1124046965 |
|
|
Aug 25 10:34:59 AM UTC 24 |
Aug 25 10:35:25 AM UTC 24 |
535452660 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.3173406164 |
|
|
Aug 25 10:35:02 AM UTC 24 |
Aug 25 10:35:27 AM UTC 24 |
803224306 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.3302659945 |
|
|
Aug 25 10:35:15 AM UTC 24 |
Aug 25 10:35:27 AM UTC 24 |
248548773 ps |
| T439 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.165926685 |
|
|
Aug 25 10:34:36 AM UTC 24 |
Aug 25 10:35:31 AM UTC 24 |
499897736 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.1115712778 |
|
|
Aug 25 10:34:24 AM UTC 24 |
Aug 25 10:35:31 AM UTC 24 |
1505856857 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.2705413354 |
|
|
Aug 25 10:35:02 AM UTC 24 |
Aug 25 10:35:32 AM UTC 24 |
6843654174 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.3822086779 |
|
|
Aug 25 10:35:25 AM UTC 24 |
Aug 25 10:35:33 AM UTC 24 |
152087526 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.2760694704 |
|
|
Aug 25 10:35:26 AM UTC 24 |
Aug 25 10:35:34 AM UTC 24 |
1070693127 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.1081472970 |
|
|
Aug 25 10:35:32 AM UTC 24 |
Aug 25 10:35:35 AM UTC 24 |
44055339 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_errors.2209839416 |
|
|
Aug 25 10:35:17 AM UTC 24 |
Aug 25 10:35:35 AM UTC 24 |
538936169 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.1583272893 |
|
|
Aug 25 10:32:29 AM UTC 24 |
Aug 25 10:35:37 AM UTC 24 |
2786111543 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.1939678620 |
|
|
Aug 25 10:35:35 AM UTC 24 |
Aug 25 10:35:38 AM UTC 24 |
28908840 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.2146143414 |
|
|
Aug 25 10:34:25 AM UTC 24 |
Aug 25 10:35:38 AM UTC 24 |
3496946591 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.2455320573 |
|
|
Aug 25 10:35:20 AM UTC 24 |
Aug 25 10:35:39 AM UTC 24 |
1204147366 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.1709031371 |
|
|
Aug 25 10:35:34 AM UTC 24 |
Aug 25 10:35:39 AM UTC 24 |
29788008 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.929747974 |
|
|
Aug 25 10:35:28 AM UTC 24 |
Aug 25 10:35:41 AM UTC 24 |
2289054305 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.1250595518 |
|
|
Aug 25 10:35:28 AM UTC 24 |
Aug 25 10:35:44 AM UTC 24 |
302204142 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.3852474282 |
|
|
Aug 25 10:35:39 AM UTC 24 |
Aug 25 10:35:44 AM UTC 24 |
457464150 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.904963368 |
|
|
Aug 25 10:35:26 AM UTC 24 |
Aug 25 10:35:45 AM UTC 24 |
367400406 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.3627492965 |
|
|
Aug 25 10:35:35 AM UTC 24 |
Aug 25 10:35:48 AM UTC 24 |
126103807 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.3680995062 |
|
|
Aug 25 10:35:39 AM UTC 24 |
Aug 25 10:35:50 AM UTC 24 |
200758113 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.2674272650 |
|
|
Aug 25 10:35:40 AM UTC 24 |
Aug 25 10:35:51 AM UTC 24 |
340428924 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.51778257 |
|
|
Aug 25 10:35:47 AM UTC 24 |
Aug 25 10:35:51 AM UTC 24 |
195612208 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.3296038340 |
|
|
Aug 25 10:35:22 AM UTC 24 |
Aug 25 10:35:51 AM UTC 24 |
1480252911 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.2803998484 |
|
|
Aug 25 10:34:54 AM UTC 24 |
Aug 25 10:35:51 AM UTC 24 |
6397249471 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.2998265332 |
|
|
Aug 25 10:34:56 AM UTC 24 |
Aug 25 10:35:52 AM UTC 24 |
316363512 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.2601837097 |
|
|
Aug 25 10:34:08 AM UTC 24 |
Aug 25 10:35:53 AM UTC 24 |
6407727532 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.2275463047 |
|
|
Aug 25 10:35:23 AM UTC 24 |
Aug 25 10:35:53 AM UTC 24 |
1407767087 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_errors.3159926292 |
|
|
Aug 25 10:35:39 AM UTC 24 |
Aug 25 10:35:54 AM UTC 24 |
439129695 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.2547251078 |
|
|
Aug 25 10:35:53 AM UTC 24 |
Aug 25 10:35:55 AM UTC 24 |
18270680 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.1505529752 |
|
|
Aug 25 10:35:54 AM UTC 24 |
Aug 25 10:35:57 AM UTC 24 |
33801121 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.3982708264 |
|
|
Aug 25 10:35:53 AM UTC 24 |
Aug 25 10:35:59 AM UTC 24 |
388522422 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.2330720243 |
|
|
Aug 25 10:35:54 AM UTC 24 |
Aug 25 10:35:59 AM UTC 24 |
132123791 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.3221032050 |
|
|
Aug 25 10:35:49 AM UTC 24 |
Aug 25 10:36:05 AM UTC 24 |
745573999 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.26413960 |
|
|
Aug 25 10:35:50 AM UTC 24 |
Aug 25 10:36:06 AM UTC 24 |
2398413881 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.2662512376 |
|
|
Aug 25 10:35:59 AM UTC 24 |
Aug 25 10:36:07 AM UTC 24 |
881247178 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.1371676700 |
|
|
Aug 25 10:35:45 AM UTC 24 |
Aug 25 10:36:07 AM UTC 24 |
8669159281 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.2434498162 |
|
|
Aug 25 10:35:42 AM UTC 24 |
Aug 25 10:36:08 AM UTC 24 |
1156775697 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.3730074096 |
|
|
Aug 25 10:35:57 AM UTC 24 |
Aug 25 10:36:09 AM UTC 24 |
491661268 ps |
| T473 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.1054372971 |
|
|
Aug 25 10:34:43 AM UTC 24 |
Aug 25 10:36:11 AM UTC 24 |
8117840157 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.3146291924 |
|
|
Aug 25 10:35:54 AM UTC 24 |
Aug 25 10:36:12 AM UTC 24 |
79340401 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.2269562521 |
|
|
Aug 25 10:34:33 AM UTC 24 |
Aug 25 10:36:12 AM UTC 24 |
2257362620 ps |
| T476 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.1576122508 |
|
|
Aug 25 10:35:48 AM UTC 24 |
Aug 25 10:36:14 AM UTC 24 |
1821442287 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.3673651222 |
|
|
Aug 25 10:35:25 AM UTC 24 |
Aug 25 10:36:14 AM UTC 24 |
9417946225 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.1933942458 |
|
|
Aug 25 10:36:13 AM UTC 24 |
Aug 25 10:36:16 AM UTC 24 |
38392247 ps |
| T479 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.3548240884 |
|
|
Aug 25 10:36:06 AM UTC 24 |
Aug 25 10:36:16 AM UTC 24 |
1834047529 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.4180218576 |
|
|
Aug 25 10:34:46 AM UTC 24 |
Aug 25 10:36:17 AM UTC 24 |
9096727920 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.1264505249 |
|
|
Aug 25 10:35:14 AM UTC 24 |
Aug 25 10:36:18 AM UTC 24 |
2932920646 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.2823038373 |
|
|
Aug 25 10:36:16 AM UTC 24 |
Aug 25 10:36:18 AM UTC 24 |
24979281 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.1757379480 |
|
|
Aug 25 10:36:08 AM UTC 24 |
Aug 25 10:36:20 AM UTC 24 |
1081390321 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.1561813631 |
|
|
Aug 25 10:36:15 AM UTC 24 |
Aug 25 10:36:20 AM UTC 24 |
129680516 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.3429201568 |
|
|
Aug 25 10:32:59 AM UTC 24 |
Aug 25 10:36:21 AM UTC 24 |
14966623299 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.2262854112 |
|
|
Aug 25 10:36:18 AM UTC 24 |
Aug 25 10:36:22 AM UTC 24 |
34843826 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_errors.671191134 |
|
|
Aug 25 10:35:55 AM UTC 24 |
Aug 25 10:36:22 AM UTC 24 |
509971919 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.1419367513 |
|
|
Aug 25 10:35:35 AM UTC 24 |
Aug 25 10:36:23 AM UTC 24 |
760770603 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.852969807 |
|
|
Aug 25 10:36:00 AM UTC 24 |
Aug 25 10:36:25 AM UTC 24 |
3236273917 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.94899466 |
|
|
Aug 25 10:36:08 AM UTC 24 |
Aug 25 10:36:27 AM UTC 24 |
947168807 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.1684965263 |
|
|
Aug 25 10:36:10 AM UTC 24 |
Aug 25 10:36:28 AM UTC 24 |
261035775 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.3933668386 |
|
|
Aug 25 10:36:26 AM UTC 24 |
Aug 25 10:36:28 AM UTC 24 |
54609958 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.500898361 |
|
|
Aug 25 10:36:08 AM UTC 24 |
Aug 25 10:36:29 AM UTC 24 |
1519783652 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.3829819004 |
|
|
Aug 25 10:36:18 AM UTC 24 |
Aug 25 10:36:29 AM UTC 24 |
254019051 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.2873675301 |
|
|
Aug 25 10:35:03 AM UTC 24 |
Aug 25 10:36:31 AM UTC 24 |
4126905845 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.2693758424 |
|
|
Aug 25 10:36:29 AM UTC 24 |
Aug 25 10:36:32 AM UTC 24 |
168794412 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.26953419 |
|
|
Aug 25 10:36:28 AM UTC 24 |
Aug 25 10:36:32 AM UTC 24 |
386357212 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.434886569 |
|
|
Aug 25 10:36:19 AM UTC 24 |
Aug 25 10:36:34 AM UTC 24 |
336223268 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.1809942073 |
|
|
Aug 25 10:36:31 AM UTC 24 |
Aug 25 10:36:34 AM UTC 24 |
86452005 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.1496509673 |
|
|
Aug 25 10:36:33 AM UTC 24 |
Aug 25 10:36:36 AM UTC 24 |
338982994 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.1967007066 |
|
|
Aug 25 10:36:20 AM UTC 24 |
Aug 25 10:36:38 AM UTC 24 |
5339155985 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.1859600408 |
|
|
Aug 25 10:36:21 AM UTC 24 |
Aug 25 10:36:41 AM UTC 24 |
1645668565 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_errors.2775271381 |
|
|
Aug 25 10:36:19 AM UTC 24 |
Aug 25 10:36:41 AM UTC 24 |
5627358333 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.2131207921 |
|
|
Aug 25 10:36:30 AM UTC 24 |
Aug 25 10:36:41 AM UTC 24 |
361257951 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.2167667213 |
|
|
Aug 25 10:36:07 AM UTC 24 |
Aug 25 10:36:42 AM UTC 24 |
4559281307 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.3672389882 |
|
|
Aug 25 10:36:42 AM UTC 24 |
Aug 25 10:36:45 AM UTC 24 |
46134300 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.3781022746 |
|
|
Aug 25 10:36:23 AM UTC 24 |
Aug 25 10:36:45 AM UTC 24 |
1629115759 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.2039835394 |
|
|
Aug 25 10:36:23 AM UTC 24 |
Aug 25 10:36:45 AM UTC 24 |
1448378933 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.1733326541 |
|
|
Aug 25 10:36:43 AM UTC 24 |
Aug 25 10:36:46 AM UTC 24 |
35772546 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.2111104509 |
|
|
Aug 25 10:33:55 AM UTC 24 |
Aug 25 10:36:46 AM UTC 24 |
5303613090 ps |
| T88 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.1473736939 |
|
|
Aug 25 10:36:42 AM UTC 24 |
Aug 25 10:36:47 AM UTC 24 |
165502366 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.2470726388 |
|
|
Aug 25 10:36:35 AM UTC 24 |
Aug 25 10:36:50 AM UTC 24 |
428351897 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.1573234236 |
|
|
Aug 25 10:36:33 AM UTC 24 |
Aug 25 10:36:51 AM UTC 24 |
2396659650 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.3066692495 |
|
|
Aug 25 10:36:48 AM UTC 24 |
Aug 25 10:36:52 AM UTC 24 |
59072433 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.832782574 |
|
|
Aug 25 10:36:46 AM UTC 24 |
Aug 25 10:36:53 AM UTC 24 |
964391823 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.3462711305 |
|
|
Aug 25 10:35:02 AM UTC 24 |
Aug 25 10:36:54 AM UTC 24 |
7536200920 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_errors.2530325929 |
|
|
Aug 25 10:36:32 AM UTC 24 |
Aug 25 10:36:54 AM UTC 24 |
399312135 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.2842302330 |
|
|
Aug 25 10:36:45 AM UTC 24 |
Aug 25 10:36:56 AM UTC 24 |
222160003 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.178735308 |
|
|
Aug 25 10:37:32 AM UTC 24 |
Aug 25 10:37:41 AM UTC 24 |
364505556 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.3491188972 |
|
|
Aug 25 10:36:35 AM UTC 24 |
Aug 25 10:36:57 AM UTC 24 |
1246952211 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.2699919988 |
|
|
Aug 25 10:36:55 AM UTC 24 |
Aug 25 10:36:58 AM UTC 24 |
18739902 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.936713873 |
|
|
Aug 25 10:36:48 AM UTC 24 |
Aug 25 10:36:59 AM UTC 24 |
335182215 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.3585948438 |
|
|
Aug 25 10:36:57 AM UTC 24 |
Aug 25 10:36:59 AM UTC 24 |
12722257 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.2066672219 |
|
|
Aug 25 10:36:55 AM UTC 24 |
Aug 25 10:36:59 AM UTC 24 |
37578875 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.3715787985 |
|
|
Aug 25 10:36:00 AM UTC 24 |
Aug 25 10:37:00 AM UTC 24 |
969858620 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.2414398725 |
|
|
Aug 25 10:36:58 AM UTC 24 |
Aug 25 10:37:02 AM UTC 24 |
24192127 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.3472492135 |
|
|
Aug 25 10:36:48 AM UTC 24 |
Aug 25 10:37:02 AM UTC 24 |
356170045 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.1646058718 |
|
|
Aug 25 10:36:37 AM UTC 24 |
Aug 25 10:37:03 AM UTC 24 |
1290284162 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/0.lc_ctrl_stress_all.3217137587 |
|
|
Aug 25 10:28:41 AM UTC 24 |
Aug 25 10:37:04 AM UTC 24 |
14265347971 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.1519965215 |
|
|
Aug 25 10:36:57 AM UTC 24 |
Aug 25 10:37:04 AM UTC 24 |
953047320 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.2116269983 |
|
|
Aug 25 10:35:40 AM UTC 24 |
Aug 25 10:37:04 AM UTC 24 |
2896643276 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.694391666 |
|
|
Aug 25 10:36:51 AM UTC 24 |
Aug 25 10:37:05 AM UTC 24 |
422631219 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.2067888669 |
|
|
Aug 25 10:37:05 AM UTC 24 |
Aug 25 10:37:08 AM UTC 24 |
15781103 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.274785256 |
|
|
Aug 25 10:35:54 AM UTC 24 |
Aug 25 10:37:09 AM UTC 24 |
290066011 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.4082409838 |
|
|
Aug 25 10:37:07 AM UTC 24 |
Aug 25 10:37:09 AM UTC 24 |
19441759 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.2044727492 |
|
|
Aug 25 10:37:00 AM UTC 24 |
Aug 25 10:37:09 AM UTC 24 |
743879245 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.381747661 |
|
|
Aug 25 10:37:01 AM UTC 24 |
Aug 25 10:37:10 AM UTC 24 |
722350257 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.1614104145 |
|
|
Aug 25 10:36:29 AM UTC 24 |
Aug 25 10:37:11 AM UTC 24 |
602122993 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.3460476984 |
|
|
Aug 25 10:37:05 AM UTC 24 |
Aug 25 10:37:11 AM UTC 24 |
247830079 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.2200474674 |
|
|
Aug 25 10:36:17 AM UTC 24 |
Aug 25 10:37:12 AM UTC 24 |
509148516 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.1003080579 |
|
|
Aug 25 10:37:00 AM UTC 24 |
Aug 25 10:37:13 AM UTC 24 |
259583751 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_errors.1763238740 |
|
|
Aug 25 10:36:47 AM UTC 24 |
Aug 25 10:37:13 AM UTC 24 |
743129206 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.1070268887 |
|
|
Aug 25 10:36:52 AM UTC 24 |
Aug 25 10:37:14 AM UTC 24 |
1955620627 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.3928686103 |
|
|
Aug 25 10:37:10 AM UTC 24 |
Aug 25 10:37:17 AM UTC 24 |
1675814408 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.1037954812 |
|
|
Aug 25 10:35:23 AM UTC 24 |
Aug 25 10:37:17 AM UTC 24 |
2368587519 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.1149830264 |
|
|
Aug 25 10:37:14 AM UTC 24 |
Aug 25 10:37:17 AM UTC 24 |
25072926 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.4070962088 |
|
|
Aug 25 10:37:03 AM UTC 24 |
Aug 25 10:37:17 AM UTC 24 |
216763410 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_errors.425133806 |
|
|
Aug 25 10:36:58 AM UTC 24 |
Aug 25 10:37:18 AM UTC 24 |
318307121 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.955889752 |
|
|
Aug 25 10:37:01 AM UTC 24 |
Aug 25 10:37:20 AM UTC 24 |
474105380 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all_with_rand_reset.1097380048 |
|
|
Aug 25 10:35:10 AM UTC 24 |
Aug 25 10:37:21 AM UTC 24 |
2215229099 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.3113440214 |
|
|
Aug 25 10:37:18 AM UTC 24 |
Aug 25 10:37:21 AM UTC 24 |
20824544 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.3384140677 |
|
|
Aug 25 10:37:12 AM UTC 24 |
Aug 25 10:37:24 AM UTC 24 |
218707609 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.4193973962 |
|
|
Aug 25 10:37:15 AM UTC 24 |
Aug 25 10:37:24 AM UTC 24 |
648589860 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.3410101235 |
|
|
Aug 25 10:37:09 AM UTC 24 |
Aug 25 10:37:25 AM UTC 24 |
97634960 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.3723182525 |
|
|
Aug 25 10:37:20 AM UTC 24 |
Aug 25 10:37:25 AM UTC 24 |
78516082 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.2791924852 |
|
|
Aug 25 10:37:12 AM UTC 24 |
Aug 25 10:37:26 AM UTC 24 |
642630188 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.1937640756 |
|
|
Aug 25 10:35:09 AM UTC 24 |
Aug 25 10:37:27 AM UTC 24 |
2691526254 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.414559304 |
|
|
Aug 25 10:37:12 AM UTC 24 |
Aug 25 10:37:27 AM UTC 24 |
781754024 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.393507215 |
|
|
Aug 25 10:37:10 AM UTC 24 |
Aug 25 10:37:27 AM UTC 24 |
886632581 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_errors.3495192994 |
|
|
Aug 25 10:37:10 AM UTC 24 |
Aug 25 10:37:28 AM UTC 24 |
718587867 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all.4248643507 |
|
|
Aug 25 10:36:12 AM UTC 24 |
Aug 25 10:37:29 AM UTC 24 |
26728933431 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.1320034365 |
|
|
Aug 25 10:37:26 AM UTC 24 |
Aug 25 10:37:29 AM UTC 24 |
62103735 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.1606797643 |
|
|
Aug 25 10:37:12 AM UTC 24 |
Aug 25 10:37:31 AM UTC 24 |
272544044 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2347514435 |
|
|
Aug 25 10:37:28 AM UTC 24 |
Aug 25 10:37:31 AM UTC 24 |
14545245 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.1840906641 |
|
|
Aug 25 10:37:18 AM UTC 24 |
Aug 25 10:37:33 AM UTC 24 |
114848574 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.3052691646 |
|
|
Aug 25 10:37:28 AM UTC 24 |
Aug 25 10:37:34 AM UTC 24 |
216244163 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.2870651592 |
|
|
Aug 25 10:35:32 AM UTC 24 |
Aug 25 10:37:34 AM UTC 24 |
34034850874 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.3381817377 |
|
|
Aug 25 10:37:22 AM UTC 24 |
Aug 25 10:37:34 AM UTC 24 |
1076483171 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.1781004160 |
|
|
Aug 25 10:37:25 AM UTC 24 |
Aug 25 10:37:35 AM UTC 24 |
411138628 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.2198426836 |
|
|
Aug 25 10:37:30 AM UTC 24 |
Aug 25 10:37:36 AM UTC 24 |
276438952 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.1523733135 |
|
|
Aug 25 10:36:45 AM UTC 24 |
Aug 25 10:37:36 AM UTC 24 |
824514361 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_errors.862161374 |
|
|
Aug 25 10:37:20 AM UTC 24 |
Aug 25 10:37:37 AM UTC 24 |
1534055468 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.819574036 |
|
|
Aug 25 10:37:22 AM UTC 24 |
Aug 25 10:37:37 AM UTC 24 |
206594165 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.3568387905 |
|
|
Aug 25 10:37:21 AM UTC 24 |
Aug 25 10:37:37 AM UTC 24 |
301742442 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.1484429747 |
|
|
Aug 25 10:37:36 AM UTC 24 |
Aug 25 10:37:39 AM UTC 24 |
39249990 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.493779755 |
|
|
Aug 25 10:37:36 AM UTC 24 |
Aug 25 10:37:39 AM UTC 24 |
11448687 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.421800690 |
|
|
Aug 25 10:37:36 AM UTC 24 |
Aug 25 10:37:39 AM UTC 24 |
17302565 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.3454943595 |
|
|
Aug 25 10:37:32 AM UTC 24 |
Aug 25 10:37:42 AM UTC 24 |
754821362 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.2125097798 |
|
|
Aug 25 10:37:30 AM UTC 24 |
Aug 25 10:37:43 AM UTC 24 |
852913981 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.637835220 |
|
|
Aug 25 10:35:45 AM UTC 24 |
Aug 25 10:37:44 AM UTC 24 |
8009591637 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.1054067645 |
|
|
Aug 25 10:37:37 AM UTC 24 |
Aug 25 10:37:44 AM UTC 24 |
297727858 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.3109822501 |
|
|
Aug 25 10:37:07 AM UTC 24 |
Aug 25 10:37:45 AM UTC 24 |
149785888 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.1658934379 |
|
|
Aug 25 10:37:30 AM UTC 24 |
Aug 25 10:37:46 AM UTC 24 |
229866176 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_errors.41882963 |
|
|
Aug 25 10:37:30 AM UTC 24 |
Aug 25 10:37:47 AM UTC 24 |
275240255 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.876118036 |
|
|
Aug 25 10:37:39 AM UTC 24 |
Aug 25 10:37:47 AM UTC 24 |
424338839 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.3086579456 |
|
|
Aug 25 10:37:18 AM UTC 24 |
Aug 25 10:37:47 AM UTC 24 |
200373507 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.2383132329 |
|
|
Aug 25 10:37:46 AM UTC 24 |
Aug 25 10:37:49 AM UTC 24 |
118237544 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3055329583 |
|
|
Aug 25 10:37:46 AM UTC 24 |
Aug 25 10:37:49 AM UTC 24 |
15387670 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all_with_rand_reset.162542890 |
|
|
Aug 25 10:34:17 AM UTC 24 |
Aug 25 10:37:51 AM UTC 24 |
4518021720 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.2200902314 |
|
|
Aug 25 10:37:32 AM UTC 24 |
Aug 25 10:37:51 AM UTC 24 |
383987152 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.2539928419 |
|
|
Aug 25 10:37:46 AM UTC 24 |
Aug 25 10:37:52 AM UTC 24 |
254962865 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.3462041444 |
|
|
Aug 25 10:37:48 AM UTC 24 |
Aug 25 10:37:53 AM UTC 24 |
176631817 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.607719678 |
|
|
Aug 25 10:37:33 AM UTC 24 |
Aug 25 10:37:54 AM UTC 24 |
575203291 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.2516139911 |
|
|
Aug 25 10:37:50 AM UTC 24 |
Aug 25 10:37:55 AM UTC 24 |
91952271 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.1597385486 |
|
|
Aug 25 10:37:40 AM UTC 24 |
Aug 25 10:37:55 AM UTC 24 |
1298302200 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.2657343471 |
|
|
Aug 25 10:37:57 AM UTC 24 |
Aug 25 10:38:45 AM UTC 24 |
290481310 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.4047433388 |
|
|
Aug 25 10:34:15 AM UTC 24 |
Aug 25 10:37:55 AM UTC 24 |
28319933287 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.1102133593 |
|
|
Aug 25 10:37:40 AM UTC 24 |
Aug 25 10:37:56 AM UTC 24 |
1415946623 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.4207217662 |
|
|
Aug 25 10:37:40 AM UTC 24 |
Aug 25 10:37:58 AM UTC 24 |
310292072 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_24/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.1860340846 |
|
|
Aug 25 10:37:48 AM UTC 24 |
Aug 25 10:37:59 AM UTC 24 |
81146951 ps |