Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	814782	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1002657

1

T1

13

T2

64

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1525274	1			T1	5		T2	70		T3	2
values[0x0]	145894	1			T1	8		T2	22		T4	58
values[0x1]	146271	1			T1	7		T2	21		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	644957	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1172482

1

T1

14

T2

75

T3

3

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6921	1			T5	2		T8	9		T17	6
valid_sources[0x01]	7039	1			T13	2		T8	3		T17	1
valid_sources[0x02]	5257	1			T16	7		T17	6		T20	6
valid_sources[0x03]	47142	1			T5	1		T8	1		T17	7
valid_sources[0x04]	5597	1			T8	2		T17	4		T20	4
valid_sources[0x05]	5737	1			T5	2		T8	1		T17	1
valid_sources[0x06]	5385	1			T17	1		T9	3		T20	3
valid_sources[0x07]	7739	1			T5	2		T17	2		T9	2
valid_sources[0x08]	7231	1			T6	2		T8	3		T17	2
valid_sources[0x09]	5497	1			T16	6		T8	2		T17	3
valid_sources[0x0a]	7000	1			T17	4		T18	1		T20	3
valid_sources[0x0b]	5717	1			T16	4		T18	1		T20	13
valid_sources[0x0c]	6169	1			T5	1		T17	3		T20	4
valid_sources[0x0d]	5545	1			T5	2		T18	1		T19	1
valid_sources[0x0e]	5698	1			T8	1		T19	3		T31	2
valid_sources[0x0f]	7453	1			T5	4		T17	2		T18	2
valid_sources[0x10]	6102	1			T8	4		T17	2		T18	1
valid_sources[0x11]	5574	1			T13	1		T17	9		T18	2
valid_sources[0x12]	6104	1			T8	3		T9	5		T20	8
valid_sources[0x13]	5814	1			T16	2		T8	2		T18	1
valid_sources[0x14]	5469	1			T17	2		T18	2		T20	4
valid_sources[0x15]	5762	1			T20	5		T31	11		T32	4
valid_sources[0x16]	5814	1			T5	1		T16	4		T8	9
valid_sources[0x17]	5759	1			T6	3		T16	5		T17	7
valid_sources[0x18]	5966	1			T5	1		T17	2		T18	1
valid_sources[0x19]	7127	1			T5	2		T16	11		T8	1
valid_sources[0x1a]	5365	1			T5	2		T17	2		T18	1
valid_sources[0x1b]	5319	1			T5	1		T8	1		T17	5
valid_sources[0x1c]	7333	1			T9	3		T20	3		T32	2
valid_sources[0x1d]	5680	1			T5	1		T8	1		T17	1
valid_sources[0x1e]	11665	1			T5	2		T17	3		T18	2
valid_sources[0x1f]	8065	1			T9	2		T20	9		T31	2
valid_sources[0x20]	7133	1			T5	2		T17	5		T18	3
valid_sources[0x21]	6014	1			T13	1		T5	1		T16	2
valid_sources[0x22]	5905	1			T17	7		T20	3		T31	5
valid_sources[0x23]	5212	1			T6	4		T8	2		T17	4
valid_sources[0x24]	5765	1			T6	1		T8	3		T18	1
valid_sources[0x25]	5749	1			T8	4		T17	8		T20	10
valid_sources[0x26]	5943	1			T5	1		T17	7		T18	1
valid_sources[0x27]	5433	1			T5	1		T18	1		T20	9
valid_sources[0x28]	7539	1			T5	2		T16	2		T8	5
valid_sources[0x29]	7898	1			T17	3		T20	4		T31	7
valid_sources[0x2a]	5901	1			T5	1		T16	3		T17	1
valid_sources[0x2b]	6083	1			T6	2		T5	1		T17	5
valid_sources[0x2c]	5812	1			T1	20		T5	2		T16	3
valid_sources[0x2d]	6285	1			T5	1		T17	2		T18	1
valid_sources[0x2e]	5431	1			T17	7		T18	1		T19	1
valid_sources[0x2f]	8985	1			T5	2		T16	4		T18	1
valid_sources[0x30]	5305	1			T5	1		T18	1		T20	7
valid_sources[0x31]	7089	1			T8	1		T17	3		T18	5
valid_sources[0x32]	6468	1			T5	2		T17	9		T18	4
valid_sources[0x33]	5426	1			T17	5		T9	1		T20	6
valid_sources[0x34]	5739	1			T8	1		T17	6		T18	1
valid_sources[0x35]	5929	1			T5	1		T17	7		T20	4
valid_sources[0x36]	5830	1			T13	4		T17	1		T18	1
valid_sources[0x37]	6451	1			T6	1		T17	2		T18	5
valid_sources[0x38]	6006	1			T6	2		T5	3		T16	1
valid_sources[0x39]	5837	1			T6	1		T5	1		T16	4
valid_sources[0x3a]	6075	1			T16	1		T17	6		T18	2
valid_sources[0x3b]	5301	1			T5	1		T17	3		T18	1
valid_sources[0x3c]	8769	1			T5	2		T8	2		T17	4
valid_sources[0x3d]	8492	1			T8	1		T17	6		T9	1
valid_sources[0x3e]	5600	1			T14	6		T5	1		T16	3
valid_sources[0x3f]	6119	1			T8	2		T17	6		T18	2
valid_sources[0x40]	5657	1			T6	5		T18	2		T20	10
valid_sources[0x41]	5390	1			T5	1		T17	2		T18	2
valid_sources[0x42]	8711	1			T18	1		T20	4		T31	10
valid_sources[0x43]	5708	1			T8	1		T17	7		T18	1
valid_sources[0x44]	10151	1			T17	7		T18	4		T20	4
valid_sources[0x45]	5514	1			T5	2		T8	2		T17	10
valid_sources[0x46]	5359	1			T16	1		T8	3		T17	3
valid_sources[0x47]	5905	1			T8	2		T17	5		T18	1
valid_sources[0x48]	5756	1			T5	1		T8	3		T17	10
valid_sources[0x49]	7146	1			T16	1		T8	3		T17	4
valid_sources[0x4a]	5875	1			T16	3		T8	1		T17	2
valid_sources[0x4b]	6438	1			T6	4		T5	1		T17	3
valid_sources[0x4c]	5737	1			T5	1		T17	4		T18	1
valid_sources[0x4d]	6642	1			T5	1		T17	1		T18	2
valid_sources[0x4e]	5402	1			T17	5		T18	1		T20	6
valid_sources[0x4f]	5699	1			T17	4		T19	1		T20	5
valid_sources[0x50]	5952	1			T5	1		T8	2		T17	4
valid_sources[0x51]	5604	1			T5	1		T17	2		T18	3
valid_sources[0x52]	6030	1			T17	3		T18	2		T20	8
valid_sources[0x53]	7465	1			T17	1		T18	1		T9	2
valid_sources[0x54]	5696	1			T5	1		T18	3		T20	5
valid_sources[0x55]	5280	1			T5	2		T16	1		T8	1
valid_sources[0x56]	5744	1			T3	3		T13	1		T16	2
valid_sources[0x57]	5623	1			T6	2		T5	3		T18	1
valid_sources[0x58]	7044	1			T5	2		T8	2		T17	3
valid_sources[0x59]	5181	1			T14	3		T5	1		T17	5
valid_sources[0x5a]	5862	1			T16	1		T18	1		T20	4
valid_sources[0x5b]	5334	1			T16	8		T8	1		T17	5
valid_sources[0x5c]	7693	1			T13	4		T16	4		T17	2
valid_sources[0x5d]	6750	1			T18	2		T19	1		T20	4
valid_sources[0x5e]	5275	1			T6	11		T5	4		T17	1
valid_sources[0x5f]	5525	1			T16	5		T17	5		T20	1
valid_sources[0x60]	10013	1			T5	1		T15	2		T8	2
valid_sources[0x61]	10317	1			T6	11		T5	1		T16	2
valid_sources[0x62]	5583	1			T9	5		T19	5		T20	4
valid_sources[0x63]	6413	1			T5	1		T17	2		T18	2
valid_sources[0x64]	7660	1			T5	1		T8	2		T17	4
valid_sources[0x65]	8869	1			T5	1		T17	6		T18	1
valid_sources[0x66]	6133	1			T18	2		T9	1		T20	5
valid_sources[0x67]	6358	1			T5	1		T8	1		T17	1
valid_sources[0x68]	6628	1			T5	1		T8	1		T17	7
valid_sources[0x69]	5249	1			T5	1		T17	3		T18	4
valid_sources[0x6a]	8972	1			T5	2		T16	2		T8	1
valid_sources[0x6b]	6291	1			T16	2		T17	2		T18	1
valid_sources[0x6c]	10822	1			T5	1		T8	3		T17	7
valid_sources[0x6d]	5508	1			T8	1		T18	2		T9	1
valid_sources[0x6e]	5820	1			T8	3		T17	3		T18	1
valid_sources[0x6f]	5813	1			T18	1		T20	2		T31	7
valid_sources[0x70]	8467	1			T8	6		T18	1		T20	5
valid_sources[0x71]	10941	1			T8	1		T17	7		T18	2
valid_sources[0x72]	5834	1			T16	1		T17	7		T18	1
valid_sources[0x73]	6162	1			T5	1		T8	2		T17	2
valid_sources[0x74]	5630	1			T17	1		T20	2		T31	3
valid_sources[0x75]	5856	1			T6	4		T5	3		T17	5
valid_sources[0x76]	7324	1			T14	4		T6	1		T5	2
valid_sources[0x77]	12306	1			T8	4		T17	3		T20	3
valid_sources[0x78]	5666	1			T5	1		T16	2		T8	3
valid_sources[0x79]	6650	1			T17	6		T20	8		T31	6
valid_sources[0x7a]	5623	1			T5	1		T17	5		T18	5
valid_sources[0x7b]	5526	1			T5	2		T17	9		T18	5
valid_sources[0x7c]	5431	1			T5	1		T17	4		T20	1
valid_sources[0x7d]	5530	1			T5	1		T17	2		T9	3
valid_sources[0x7e]	5612	1			T8	2		T17	1		T18	1
valid_sources[0x7f]	6553	1			T5	3		T17	2		T18	1
valid_sources[0x80]	25027	1			T16	3		T8	4		T17	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

751467

1

T1

2

T2

30

T3

1

values[0x0]

all_enables

biggest_size

126325

1

T1

6

T2

18

T4

55

values[0x1]

all_enables

biggest_size

124865

1

T1

5

T2

16

T3

1