Unified Coverage Report :: Module :: prim_sync_reqack_data

Module : prim_sync_reqack_data

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_sync_reqack_data.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_lc_ctrl_kmac_if.u_prim_sync_reqack_data_in

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.41	98.18	100.00			95.45	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	100.00		83.33	100.00	100.00	u_lc_ctrl_kmac_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_sync_reqack	98.16	97.92	100.00			94.74	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
CONT_ASSIGN	80	1	1	100.00
CONT_ASSIGN	81	1	1	100.00
ALWAYS	83	4	4	100.00
CONT_ASSIGN	89	1	1	100.00

79                          // Sample the data when seing the REQ/ACK handshake in the DST domain.
80         1/1              assign data_we = dst_req_o & dst_ack_i;
           Tests:       T1 T2 T3 
81         1/1              assign data_d  = data_i;
           Tests:       T1 T2 T3 
82                          always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
83         1/1                if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
84         1/1                  data_q <= '0;
           Tests:       T1 T2 T3 
85         1/1                end else if (data_we) begin
           Tests:       T1 T2 T3 
86         1/1                  data_q <= data_d;
           Tests:       T2 T5 T7 
87                            end
                        MISSING_ELSE
88                          end
89         1/1              assign data_o = data_q;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_sync_reqack_data

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       80
 EXPRESSION (dst_req_o & dst_ack_i)
             ----1----   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T20,T60,T34
1	0	Covered	T2,T5,T7
1	1	Covered	T2,T5,T7

---

Branch Coverage for Module : prim_sync_reqack_data

	Line No.	Total	Covered	Percent
Branches		3	3	100.00
IF	83	3	3	100.00

83               if (!rst_dst_ni) begin
                 -1-  
84                 data_q <= '0;
                   ==>
85               end else if (data_we) begin
                          -2-  
86                 data_q <= data_d;
                   ==>
87               end
                 MISSING_ELSE
                 ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T5,T7
0	0	Covered	T1,T2,T3