Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_26/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	58616305	12632	0	0
claim_transition_if_regwen_rd_A	58616305	1991	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58616305	12632	0	0
T29	17843	0	0	0
T96	209568	4	0	0
T97	0	6	0	0
T98	0	12	0	0
T152	0	11	0	0
T154	0	4	0	0
T155	0	6	0	0
T156	0	10	0	0
T157	0	2	0	0
T158	0	3	0	0
T159	0	13	0	0
T160	1810	0	0	0
T161	7136	0	0	0
T162	36051	0	0	0
T163	47677	0	0	0
T164	29019	0	0	0
T165	1318	0	0	0
T166	2284	0	0	0
T167	26570	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	58616305	1991	0	0
T78	579323	0	0	0
T114	0	5	0	0
T115	0	77	0	0
T121	0	125	0	0
T122	0	15	0	0
T128	0	36	0	0
T148	0	7	0	0
T168	160271	1	0	0
T169	0	7	0	0
T170	0	3	0	0
T171	0	7	0	0
T172	23603	0	0	0
T173	19208	0	0	0
T174	1243	0	0	0
T175	2233	0	0	0
T176	24706	0	0	0
T177	228236	0	0	0
T178	31568	0	0	0
T179	6502	0	0	0