Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	678075	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

868029

1

T1

12

T2

1503

T3

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1249103	1			T1	51		T2	2848		T3	2
values[0x0]	148277	1			T1	7		T2	73		T4	78
values[0x1]	148724	1			T1	9		T2	79		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	534821	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1011283

1

T1

32

T2

1793

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3936	1			T2	100		T5	1		T15	14
valid_sources[0x01]	3987	1			T2	35		T5	1		T9	2
valid_sources[0x02]	3877	1			T5	1		T9	3		T15	14
valid_sources[0x03]	4202	1			T2	13		T9	4		T15	15
valid_sources[0x04]	5442	1			T5	4		T15	16		T17	4
valid_sources[0x05]	4085	1			T5	2		T15	12		T17	10
valid_sources[0x06]	6539	1			T2	29		T5	2		T14	1494
valid_sources[0x07]	4332	1			T2	1		T5	1		T9	1
valid_sources[0x08]	4885	1			T5	5		T15	14		T22	1
valid_sources[0x09]	4814	1			T5	3		T15	21		T22	2
valid_sources[0x0a]	9178	1			T2	44		T5	3		T15	10
valid_sources[0x0b]	3948	1			T2	14		T6	3		T5	1
valid_sources[0x0c]	4216	1			T15	9		T17	6		T18	5
valid_sources[0x0d]	4135	1			T2	34		T15	8		T17	5
valid_sources[0x0e]	5645	1			T2	21		T15	17		T17	2
valid_sources[0x0f]	4100	1			T1	8		T2	28		T5	4
valid_sources[0x10]	3975	1			T2	35		T5	2		T9	2
valid_sources[0x11]	4018	1			T2	1		T5	2		T15	20
valid_sources[0x12]	3993	1			T2	49		T5	1		T9	3
valid_sources[0x13]	3956	1			T5	7		T15	17		T17	4
valid_sources[0x14]	6613	1			T5	1		T15	14		T17	3
valid_sources[0x15]	4301	1			T2	33		T9	2		T15	12
valid_sources[0x16]	3923	1			T2	2		T5	1		T15	10
valid_sources[0x17]	3943	1			T9	5		T15	10		T17	7
valid_sources[0x18]	4187	1			T2	3		T5	1		T9	5
valid_sources[0x19]	5154	1			T2	23		T5	7		T15	19
valid_sources[0x1a]	3854	1			T2	42		T5	1		T15	9
valid_sources[0x1b]	3980	1			T5	1		T15	14		T17	7
valid_sources[0x1c]	6723	1			T5	1		T15	5		T22	1
valid_sources[0x1d]	3831	1			T2	3		T15	20		T17	4
valid_sources[0x1e]	5423	1			T5	2		T15	8		T17	5
valid_sources[0x1f]	5088	1			T5	1		T15	21		T17	10
valid_sources[0x20]	7042	1			T2	22		T15	14		T22	1
valid_sources[0x21]	4169	1			T2	14		T5	7		T15	17
valid_sources[0x22]	5356	1			T2	1		T6	1		T5	2
valid_sources[0x23]	5422	1			T9	1		T15	19		T17	3
valid_sources[0x24]	3984	1			T2	5		T15	13		T17	3
valid_sources[0x25]	4472	1			T2	24		T5	5		T9	2
valid_sources[0x26]	4403	1			T2	28		T15	15		T17	1
valid_sources[0x27]	14355	1			T2	5		T5	2		T15	12
valid_sources[0x28]	6120	1			T2	29		T5	8		T15	7
valid_sources[0x29]	3890	1			T2	24		T5	3		T15	14
valid_sources[0x2a]	6114	1			T15	12		T17	2		T47	11
valid_sources[0x2b]	4340	1			T6	2		T9	5		T15	16
valid_sources[0x2c]	4078	1			T2	9		T9	1		T15	15
valid_sources[0x2d]	4552	1			T2	56		T5	7		T15	16
valid_sources[0x2e]	4130	1			T9	3		T15	6		T17	4
valid_sources[0x2f]	4093	1			T2	17		T5	2		T15	19
valid_sources[0x30]	11699	1			T4	12		T15	18		T22	1
valid_sources[0x31]	7331	1			T5	4		T15	17		T22	2
valid_sources[0x32]	4467	1			T2	6		T15	9		T22	1
valid_sources[0x33]	4250	1			T9	1		T15	6		T17	5
valid_sources[0x34]	5138	1			T5	11		T9	1		T15	14
valid_sources[0x35]	4766	1			T2	25		T5	3		T9	3
valid_sources[0x36]	5831	1			T2	49		T5	7		T15	13
valid_sources[0x37]	4112	1			T1	7		T2	13		T9	5
valid_sources[0x38]	5578	1			T5	3		T15	12		T17	7
valid_sources[0x39]	3964	1			T2	2		T5	2		T15	12
valid_sources[0x3a]	10022	1			T2	1		T5	1		T15	11
valid_sources[0x3b]	4154	1			T2	30		T5	2		T15	7
valid_sources[0x3c]	5258	1			T4	32		T6	3		T5	3
valid_sources[0x3d]	3990	1			T15	11		T17	5		T18	3
valid_sources[0x3e]	4048	1			T2	18		T5	8		T15	11
valid_sources[0x3f]	4211	1			T5	2		T15	19		T17	4
valid_sources[0x40]	3882	1			T2	3		T5	1		T15	14
valid_sources[0x41]	5293	1			T5	4		T9	4		T15	16
valid_sources[0x42]	5237	1			T5	1		T15	12		T17	4
valid_sources[0x43]	4313	1			T2	12		T5	3		T9	1
valid_sources[0x44]	3902	1			T2	22		T15	18		T17	4
valid_sources[0x45]	4116	1			T5	2		T9	11		T15	9
valid_sources[0x46]	4232	1			T2	14		T15	11		T17	7
valid_sources[0x47]	4331	1			T2	13		T5	1		T15	14
valid_sources[0x48]	5554	1			T6	1		T15	14		T17	2
valid_sources[0x49]	3895	1			T2	37		T5	2		T15	10
valid_sources[0x4a]	14014	1			T5	1		T15	25		T17	6
valid_sources[0x4b]	13023	1			T2	11		T5	3		T15	12
valid_sources[0x4c]	4071	1			T2	18		T5	6		T15	16
valid_sources[0x4d]	4115	1			T5	1		T9	5		T15	18
valid_sources[0x4e]	4230	1			T2	13		T15	13		T17	4
valid_sources[0x4f]	7441	1			T4	1		T5	2		T15	11
valid_sources[0x50]	3988	1			T5	1		T15	9		T17	2
valid_sources[0x51]	3784	1			T5	2		T9	3		T15	20
valid_sources[0x52]	23353	1			T2	3		T5	3		T9	1
valid_sources[0x53]	18237	1			T2	24		T5	4		T15	11
valid_sources[0x54]	4010	1			T2	10		T5	2		T15	21
valid_sources[0x55]	5965	1			T2	9		T5	2		T15	13
valid_sources[0x56]	3818	1			T15	6		T17	8		T18	4
valid_sources[0x57]	3957	1			T5	3		T9	1		T15	9
valid_sources[0x58]	3862	1			T2	22		T5	1		T15	16
valid_sources[0x59]	6761	1			T2	3		T5	1		T15	20
valid_sources[0x5a]	3867	1			T2	7		T4	6		T5	3
valid_sources[0x5b]	4168	1			T5	3		T9	4		T15	20
valid_sources[0x5c]	4137	1			T2	8		T4	32		T5	4
valid_sources[0x5d]	3693	1			T5	1		T15	10		T17	2
valid_sources[0x5e]	3973	1			T5	1		T9	4		T15	10
valid_sources[0x5f]	4092	1			T2	8		T4	3		T5	1
valid_sources[0x60]	4013	1			T2	58		T15	12		T17	9
valid_sources[0x61]	5245	1			T2	3		T5	3		T15	13
valid_sources[0x62]	4039	1			T2	6		T9	8		T15	12
valid_sources[0x63]	5927	1			T2	20		T6	2		T15	10
valid_sources[0x64]	7731	1			T2	72		T5	1		T9	2
valid_sources[0x65]	5967	1			T2	1		T15	14		T17	1
valid_sources[0x66]	3967	1			T2	42		T9	1		T15	11
valid_sources[0x67]	32495	1			T2	1		T5	6		T15	14
valid_sources[0x68]	4982	1			T2	2		T5	1		T15	9
valid_sources[0x69]	4309	1			T2	40		T5	2		T15	15
valid_sources[0x6a]	4204	1			T4	6		T5	1		T15	15
valid_sources[0x6b]	4179	1			T15	12		T17	3		T18	3
valid_sources[0x6c]	5526	1			T2	31		T5	3		T9	7
valid_sources[0x6d]	4152	1			T5	5		T15	12		T17	8
valid_sources[0x6e]	7316	1			T2	12		T6	2		T9	1
valid_sources[0x6f]	3899	1			T5	2		T15	16		T22	1
valid_sources[0x70]	4408	1			T5	2		T9	1		T15	8
valid_sources[0x71]	4028	1			T15	18		T17	5		T18	4
valid_sources[0x72]	5271	1			T2	30		T15	14		T17	7
valid_sources[0x73]	3822	1			T2	20		T5	4		T9	1
valid_sources[0x74]	4276	1			T4	97		T15	13		T22	1
valid_sources[0x75]	3814	1			T3	3		T9	2		T15	12
valid_sources[0x76]	3948	1			T2	7		T5	4		T15	13
valid_sources[0x77]	5927	1			T2	5		T5	1		T15	11
valid_sources[0x78]	5135	1			T2	10		T5	2		T9	3
valid_sources[0x79]	4077	1			T2	37		T5	2		T15	11
valid_sources[0x7a]	3944	1			T2	24		T5	3		T15	9
valid_sources[0x7b]	194413	1			T2	18		T5	6		T15	12
valid_sources[0x7c]	4403	1			T2	13		T6	1		T5	2
valid_sources[0x7d]	26129	1			T15	6		T17	6		T18	2
valid_sources[0x7e]	3958	1			T5	3		T9	4		T15	12
valid_sources[0x7f]	6558	1			T2	29		T5	2		T15	11
valid_sources[0x80]	3959	1			T1	1		T5	1		T15	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

612444

1

T1

1

T2

1378

T3

1

values[0x0]

all_enables

biggest_size

128497

1

T1

3

T2

59

T4

71

values[0x1]

all_enables

biggest_size

127088

1

T1

8

T2

66

T4

59