Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	57264762	16379	0	0
claim_transition_if_regwen_rd_A	57264762	1100	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57264762	16379	0	0
T28	24114	0	0	0
T99	296595	4	0	0
T100	0	8	0	0
T101	0	6	0	0
T144	0	4	0	0
T145	0	2	0	0
T146	0	7	0	0
T147	0	7	0	0
T148	0	13	0	0
T149	0	2	0	0
T150	0	2	0	0
T151	161546	0	0	0
T152	11442	0	0	0
T153	17814	0	0	0
T154	8580	0	0	0
T155	29581	0	0	0
T156	27466	0	0	0
T157	329241	0	0	0
T158	21976	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57264762	1100	0	0
T113	0	43	0	0
T114	0	66	0	0
T150	29495	3	0	0
T159	0	1	0	0
T160	0	12	0	0
T161	0	13	0	0
T162	0	5	0	0
T163	0	220	0	0
T164	0	32	0	0
T165	0	17	0	0
T166	2140	0	0	0
T167	24287	0	0	0
T168	39621	0	0	0
T169	33454	0	0	0
T170	1286	0	0	0
T171	2158	0	0	0
T172	19196	0	0	0
T173	4530	0	0	0
T174	36908	0	0	0