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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.25 97.99 95.77 93.40 100.00 98.55 98.76 96.29


Total test records in report: 999
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T379 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_alert_test.4036533415 Aug 29 12:54:44 PM UTC 24 Aug 29 12:54:46 PM UTC 24 72845015 ps
T380 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_errors.3115803314 Aug 29 12:54:32 PM UTC 24 Aug 29 12:54:47 PM UTC 24 274255579 ps
T59 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_volatile_unlock_smoke.2196979198 Aug 29 12:54:45 PM UTC 24 Aug 29 12:54:48 PM UTC 24 16063090 ps
T381 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_errors.2891735546 Aug 29 12:54:23 PM UTC 24 Aug 29 12:54:48 PM UTC 24 461990736 ps
T382 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_smoke.3655501039 Aug 29 12:54:45 PM UTC 24 Aug 29 12:54:48 PM UTC 24 167520411 ps
T239 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_security_escalation.1002330122 Aug 29 12:54:34 PM UTC 24 Aug 29 12:54:49 PM UTC 24 1526406848 ps
T383 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_mux.471748912 Aug 29 12:54:40 PM UTC 24 Aug 29 12:54:49 PM UTC 24 627413997 ps
T384 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_post_trans.1218150106 Aug 29 12:54:24 PM UTC 24 Aug 29 12:54:50 PM UTC 24 2326797556 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_prog_failure.36428474 Aug 29 12:54:46 PM UTC 24 Aug 29 12:54:50 PM UTC 24 34143596 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_prog_failure.2615359064 Aug 29 12:54:35 PM UTC 24 Aug 29 12:54:50 PM UTC 24 4634402028 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_token_digest.2501809760 Aug 29 12:54:40 PM UTC 24 Aug 29 12:54:51 PM UTC 24 771279240 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_sec_token_digest.3087091761 Aug 29 12:54:27 PM UTC 24 Aug 29 12:54:53 PM UTC 24 778331129 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_errors.833586666 Aug 29 12:53:47 PM UTC 24 Aug 29 12:54:53 PM UTC 24 4815986811 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_post_trans.2328927657 Aug 29 12:54:46 PM UTC 24 Aug 29 12:54:56 PM UTC 24 227736331 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_access.3331904714 Aug 29 12:54:50 PM UTC 24 Aug 29 12:54:56 PM UTC 24 185789228 ps
T391 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_smoke.1866792185 Aug 29 12:54:48 PM UTC 24 Aug 29 12:54:57 PM UTC 24 820464053 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_alert_test.2639271438 Aug 29 12:54:55 PM UTC 24 Aug 29 12:54:58 PM UTC 24 139890304 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_jtag_state_failure.3290966218 Aug 29 12:53:47 PM UTC 24 Aug 29 12:54:58 PM UTC 24 16337090571 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_errors.240138159 Aug 29 12:54:47 PM UTC 24 Aug 29 12:54:59 PM UTC 24 220180006 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_sec_mubi.2944996239 Aug 29 12:54:37 PM UTC 24 Aug 29 12:54:59 PM UTC 24 1596751176 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_volatile_unlock_smoke.452250788 Aug 29 12:54:57 PM UTC 24 Aug 29 12:54:59 PM UTC 24 39056403 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_post_trans.545935503 Aug 29 12:54:35 PM UTC 24 Aug 29 12:54:59 PM UTC 24 4031323856 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_prog_failure.989483760 Aug 29 12:54:50 PM UTC 24 Aug 29 12:55:00 PM UTC 24 460975512 ps
T399 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_state_failure.2732303125 Aug 29 12:54:30 PM UTC 24 Aug 29 12:55:00 PM UTC 24 264907628 ps
T400 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_prog_failure.2617725326 Aug 29 12:54:59 PM UTC 24 Aug 29 12:55:02 PM UTC 24 294343388 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_smoke.1095005368 Aug 29 12:54:56 PM UTC 24 Aug 29 12:55:02 PM UTC 24 91054131 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_errors.555771824 Aug 29 12:54:26 PM UTC 24 Aug 29 12:55:03 PM UTC 24 4652446576 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_errors.1118667839 Aug 29 12:55:08 PM UTC 24 Aug 29 12:55:25 PM UTC 24 993723747 ps
T404 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_post_trans.3282700041 Aug 29 12:54:50 PM UTC 24 Aug 29 12:55:03 PM UTC 24 1845610349 ps
T405 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_mux.1578916891 Aug 29 12:54:52 PM UTC 24 Aug 29 12:55:04 PM UTC 24 307150632 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_prog_failure.767180955 Aug 29 12:55:00 PM UTC 24 Aug 29 12:55:04 PM UTC 24 86086637 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_token_digest.830453623 Aug 29 12:54:52 PM UTC 24 Aug 29 12:55:04 PM UTC 24 1105973161 ps
T408 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_sec_mubi.606325518 Aug 29 12:54:50 PM UTC 24 Aug 29 12:55:05 PM UTC 24 315477889 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_smoke.3713638296 Aug 29 12:55:00 PM UTC 24 Aug 29 12:55:05 PM UTC 24 206378718 ps
T410 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_alert_test.4113600406 Aug 29 12:55:05 PM UTC 24 Aug 29 12:55:08 PM UTC 24 82596053 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_smoke.3024196629 Aug 29 12:55:05 PM UTC 24 Aug 29 12:55:08 PM UTC 24 48026742 ps
T240 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_security_escalation.1159025723 Aug 29 12:54:48 PM UTC 24 Aug 29 12:55:09 PM UTC 24 1560210534 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_volatile_unlock_smoke.901183546 Aug 29 12:55:07 PM UTC 24 Aug 29 12:55:09 PM UTC 24 24108818 ps
T413 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_state_failure.3594805053 Aug 29 12:54:13 PM UTC 24 Aug 29 12:55:11 PM UTC 24 28938585303 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/2.lc_ctrl_stress_all.1819851324 Aug 29 12:52:19 PM UTC 24 Aug 29 12:55:11 PM UTC 24 11301378004 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_prog_failure.1913364526 Aug 29 12:55:07 PM UTC 24 Aug 29 12:55:11 PM UTC 24 336504410 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_smoke.4169972972 Aug 29 12:55:19 PM UTC 24 Aug 29 12:55:25 PM UTC 24 420797299 ps
T416 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_post_trans.2254006054 Aug 29 12:54:59 PM UTC 24 Aug 29 12:55:11 PM UTC 24 274005312 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_access.4099000465 Aug 29 12:55:03 PM UTC 24 Aug 29 12:55:12 PM UTC 24 325252930 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_security_escalation.2205835534 Aug 29 12:55:00 PM UTC 24 Aug 29 12:55:13 PM UTC 24 343409353 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_jtag_errors.4192471987 Aug 29 12:54:17 PM UTC 24 Aug 29 12:55:14 PM UTC 24 5932169232 ps
T420 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_post_trans.4227990443 Aug 29 12:55:00 PM UTC 24 Aug 29 12:55:14 PM UTC 24 1928004451 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_access.627059414 Aug 29 12:55:13 PM UTC 24 Aug 29 12:55:15 PM UTC 24 855773526 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_mux.2033092096 Aug 29 12:55:04 PM UTC 24 Aug 29 12:55:15 PM UTC 24 252155805 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/4.lc_ctrl_stress_all.2841396599 Aug 29 12:52:54 PM UTC 24 Aug 29 12:55:16 PM UTC 24 4521297933 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all.4289792288 Aug 29 12:54:41 PM UTC 24 Aug 29 12:55:17 PM UTC 24 3376032154 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_smoke.3571864111 Aug 29 12:55:10 PM UTC 24 Aug 29 12:55:17 PM UTC 24 243444051 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_alert_test.2813426377 Aug 29 12:55:16 PM UTC 24 Aug 29 12:55:18 PM UTC 24 20837814 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_token_digest.3848112917 Aug 29 12:55:04 PM UTC 24 Aug 29 12:55:18 PM UTC 24 653815096 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_smoke.1064280890 Aug 29 12:55:16 PM UTC 24 Aug 29 12:55:18 PM UTC 24 22783842 ps
T429 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_security_escalation.539959621 Aug 29 12:55:10 PM UTC 24 Aug 29 12:55:19 PM UTC 24 325703732 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_state_failure.1297228264 Aug 29 12:54:46 PM UTC 24 Aug 29 12:55:19 PM UTC 24 513622956 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_volatile_unlock_smoke.3395144396 Aug 29 12:55:18 PM UTC 24 Aug 29 12:55:20 PM UTC 24 47904010 ps
T432 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_prog_failure.624092338 Aug 29 12:55:18 PM UTC 24 Aug 29 12:55:21 PM UTC 24 71024952 ps
T433 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_prog_failure.151641489 Aug 29 12:55:13 PM UTC 24 Aug 29 12:55:22 PM UTC 24 1309232000 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_post_trans.630245661 Aug 29 12:55:07 PM UTC 24 Aug 29 12:55:23 PM UTC 24 111109693 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_sec_mubi.3791795899 Aug 29 12:55:04 PM UTC 24 Aug 29 12:55:23 PM UTC 24 1080883558 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_errors.510519653 Aug 29 12:54:50 PM UTC 24 Aug 29 12:55:24 PM UTC 24 13671310292 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_state_failure.3144110382 Aug 29 12:54:59 PM UTC 24 Aug 29 12:55:24 PM UTC 24 762929461 ps
T104 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_state_failure.619779854 Aug 29 12:54:34 PM UTC 24 Aug 29 12:55:25 PM UTC 24 1076451437 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/10.lc_ctrl_stress_all.496214570 Aug 29 12:54:20 PM UTC 24 Aug 29 12:55:25 PM UTC 24 2156168273 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_mux.3072432260 Aug 29 12:55:13 PM UTC 24 Aug 29 12:55:25 PM UTC 24 941495708 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_smoke.2559374531 Aug 29 12:55:27 PM UTC 24 Aug 29 12:55:33 PM UTC 24 93787039 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_post_trans.41244292 Aug 29 12:55:10 PM UTC 24 Aug 29 12:55:26 PM UTC 24 1725501281 ps
T442 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_jtag_state_failure.3321871734 Aug 29 12:54:24 PM UTC 24 Aug 29 12:55:27 PM UTC 24 1194673987 ps
T443 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_prog_failure.3965876019 Aug 29 12:55:20 PM UTC 24 Aug 29 12:55:27 PM UTC 24 154678208 ps
T444 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_access.1717346692 Aug 29 12:55:23 PM UTC 24 Aug 29 12:55:28 PM UTC 24 144369099 ps
T445 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_alert_test.2606761196 Aug 29 12:55:25 PM UTC 24 Aug 29 12:55:28 PM UTC 24 14996175 ps
T446 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_volatile_unlock_smoke.353706217 Aug 29 12:55:27 PM UTC 24 Aug 29 12:55:29 PM UTC 24 21568225 ps
T447 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_token_digest.2200363041 Aug 29 12:55:14 PM UTC 24 Aug 29 12:55:30 PM UTC 24 1180364087 ps
T448 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_post_trans.3285617162 Aug 29 12:55:20 PM UTC 24 Aug 29 12:55:30 PM UTC 24 365487195 ps
T449 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_security_escalation.3346640266 Aug 29 12:55:19 PM UTC 24 Aug 29 12:55:31 PM UTC 24 361837322 ps
T450 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_prog_failure.2635207701 Aug 29 12:55:27 PM UTC 24 Aug 29 12:55:31 PM UTC 24 46924263 ps
T451 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_mubi.527976910 Aug 29 12:55:23 PM UTC 24 Aug 29 12:55:32 PM UTC 24 196515734 ps
T452 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_sec_mubi.2657184880 Aug 29 12:55:13 PM UTC 24 Aug 29 12:55:33 PM UTC 24 625277291 ps
T453 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_post_trans.1773903905 Aug 29 12:55:18 PM UTC 24 Aug 29 12:55:33 PM UTC 24 327537814 ps
T454 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_smoke.2997248582 Aug 29 12:55:29 PM UTC 24 Aug 29 12:55:35 PM UTC 24 134747415 ps
T455 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_access.1600818816 Aug 29 12:55:32 PM UTC 24 Aug 29 12:55:36 PM UTC 24 1089460706 ps
T456 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_digest.2367346120 Aug 29 12:55:24 PM UTC 24 Aug 29 12:55:37 PM UTC 24 254319058 ps
T457 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_state_failure.3105677914 Aug 29 12:55:07 PM UTC 24 Aug 29 12:55:37 PM UTC 24 256542751 ps
T458 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_alert_test.3337569082 Aug 29 12:55:35 PM UTC 24 Aug 29 12:55:37 PM UTC 24 23744342 ps
T459 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_state_failure.577392665 Aug 29 12:55:00 PM UTC 24 Aug 29 12:55:38 PM UTC 24 1152687855 ps
T460 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_post_trans.541149555 Aug 29 12:55:27 PM UTC 24 Aug 29 12:55:39 PM UTC 24 68803047 ps
T461 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_sec_token_mux.3440815660 Aug 29 12:55:24 PM UTC 24 Aug 29 12:55:39 PM UTC 24 664031518 ps
T462 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_volatile_unlock_smoke.3963461811 Aug 29 12:55:37 PM UTC 24 Aug 29 12:55:39 PM UTC 24 32293624 ps
T463 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_errors.3550657135 Aug 29 12:55:13 PM UTC 24 Aug 29 12:55:40 PM UTC 24 1385632003 ps
T464 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_smoke.573591372 Aug 29 12:55:36 PM UTC 24 Aug 29 12:55:40 PM UTC 24 232964983 ps
T465 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_errors.837647998 Aug 29 12:55:28 PM UTC 24 Aug 29 12:55:41 PM UTC 24 972480689 ps
T466 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_security_escalation.617278612 Aug 29 12:55:28 PM UTC 24 Aug 29 12:55:41 PM UTC 24 750980867 ps
T467 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_prog_failure.1957576976 Aug 29 12:55:38 PM UTC 24 Aug 29 12:55:43 PM UTC 24 280082762 ps
T468 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_digest.1024312267 Aug 29 12:55:33 PM UTC 24 Aug 29 12:55:43 PM UTC 24 260670471 ps
T469 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_post_trans.4154654615 Aug 29 12:55:38 PM UTC 24 Aug 29 12:55:43 PM UTC 24 90499334 ps
T100 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_stress_all_with_rand_reset.3113099165 Aug 29 12:54:41 PM UTC 24 Aug 29 12:55:44 PM UTC 24 3921658190 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_prog_failure.4029860895 Aug 29 12:55:30 PM UTC 24 Aug 29 12:55:44 PM UTC 24 467810291 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_jtag_state_failure.3594081047 Aug 29 12:54:50 PM UTC 24 Aug 29 12:55:45 PM UTC 24 2596175608 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_mubi.695211634 Aug 29 12:55:33 PM UTC 24 Aug 29 12:55:45 PM UTC 24 248437225 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/12.lc_ctrl_jtag_errors.258411902 Aug 29 12:54:37 PM UTC 24 Aug 29 12:55:46 PM UTC 24 9232922264 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_digest.178598456 Aug 29 12:55:59 PM UTC 24 Aug 29 12:56:09 PM UTC 24 292160405 ps
T193 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_alert_test.3000224610 Aug 29 12:55:45 PM UTC 24 Aug 29 12:55:47 PM UTC 24 35976099 ps
T194 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_sec_token_mux.1886224602 Aug 29 12:55:33 PM UTC 24 Aug 29 12:55:48 PM UTC 24 1557598967 ps
T195 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_volatile_unlock_smoke.217071329 Aug 29 12:55:46 PM UTC 24 Aug 29 12:55:49 PM UTC 24 11829284 ps
T196 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_smoke.1308089965 Aug 29 12:55:40 PM UTC 24 Aug 29 12:55:49 PM UTC 24 1315528122 ps
T470 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_errors.1373827544 Aug 29 12:55:38 PM UTC 24 Aug 29 12:55:49 PM UTC 24 791236298 ps
T471 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_errors.2404228630 Aug 29 12:55:19 PM UTC 24 Aug 29 12:55:50 PM UTC 24 535155620 ps
T472 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_smoke.557093373 Aug 29 12:55:45 PM UTC 24 Aug 29 12:55:50 PM UTC 24 37909467 ps
T473 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_state_failure.2026544381 Aug 29 12:55:27 PM UTC 24 Aug 29 12:55:51 PM UTC 24 496946433 ps
T474 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_access.1411295637 Aug 29 12:55:42 PM UTC 24 Aug 29 12:55:51 PM UTC 24 369294965 ps
T475 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_prog_failure.406642746 Aug 29 12:55:41 PM UTC 24 Aug 29 12:55:51 PM UTC 24 1227495415 ps
T476 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_state_failure.567767596 Aug 29 12:55:18 PM UTC 24 Aug 29 12:55:52 PM UTC 24 659279144 ps
T477 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_post_trans.14485514 Aug 29 12:55:30 PM UTC 24 Aug 29 12:55:53 PM UTC 24 1563876865 ps
T478 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_prog_failure.2050342573 Aug 29 12:55:48 PM UTC 24 Aug 29 12:55:53 PM UTC 24 192684735 ps
T479 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_jtag_state_failure.224915416 Aug 29 12:53:58 PM UTC 24 Aug 29 12:55:54 PM UTC 24 12211621067 ps
T480 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_security_escalation.2135475412 Aug 29 12:55:40 PM UTC 24 Aug 29 12:55:54 PM UTC 24 1572477032 ps
T481 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_digest.3461634948 Aug 29 12:55:44 PM UTC 24 Aug 29 12:55:55 PM UTC 24 251645927 ps
T482 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_token_mux.1718234694 Aug 29 12:55:44 PM UTC 24 Aug 29 12:55:56 PM UTC 24 3592907514 ps
T81 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_alert_test.943596565 Aug 29 12:55:54 PM UTC 24 Aug 29 12:55:57 PM UTC 24 28227305 ps
T483 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_access.378966605 Aug 29 12:55:52 PM UTC 24 Aug 29 12:55:57 PM UTC 24 138236661 ps
T484 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_volatile_unlock_smoke.1137953690 Aug 29 12:55:55 PM UTC 24 Aug 29 12:55:57 PM UTC 24 81890770 ps
T485 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_state_failure.2953183565 Aug 29 12:55:19 PM UTC 24 Aug 29 12:55:57 PM UTC 24 1205345700 ps
T486 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_post_trans.269987274 Aug 29 12:55:48 PM UTC 24 Aug 29 12:55:57 PM UTC 24 319861369 ps
T487 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_smoke.2664547006 Aug 29 12:55:54 PM UTC 24 Aug 29 12:55:58 PM UTC 24 554992553 ps
T488 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_smoke.1244455444 Aug 29 12:55:50 PM UTC 24 Aug 29 12:55:59 PM UTC 24 727453103 ps
T489 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_jtag_state_failure.449200362 Aug 29 12:55:10 PM UTC 24 Aug 29 12:56:01 PM UTC 24 1126145274 ps
T101 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all_with_rand_reset.1737460690 Aug 29 12:54:27 PM UTC 24 Aug 29 12:56:01 PM UTC 24 1793364244 ps
T490 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_jtag_errors.2279510415 Aug 29 12:55:02 PM UTC 24 Aug 29 12:56:01 PM UTC 24 7685365413 ps
T491 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/11.lc_ctrl_stress_all.4175625913 Aug 29 12:54:27 PM UTC 24 Aug 29 12:56:01 PM UTC 24 3447348348 ps
T492 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_errors.1636000655 Aug 29 12:55:48 PM UTC 24 Aug 29 12:56:02 PM UTC 24 665577716 ps
T493 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_mubi.89367917 Aug 29 12:55:52 PM UTC 24 Aug 29 12:56:09 PM UTC 24 1395900995 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_sec_mubi.3272230090 Aug 29 12:55:42 PM UTC 24 Aug 29 12:56:02 PM UTC 24 3314408711 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_security_escalation.957418440 Aug 29 12:55:49 PM UTC 24 Aug 29 12:56:03 PM UTC 24 790665820 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_prog_failure.358343995 Aug 29 12:55:58 PM UTC 24 Aug 29 12:56:03 PM UTC 24 66492393 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_post_trans.3878903043 Aug 29 12:55:40 PM UTC 24 Aug 29 12:56:04 PM UTC 24 2109640273 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_alert_test.3809193583 Aug 29 12:56:02 PM UTC 24 Aug 29 12:56:05 PM UTC 24 21947966 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_digest.2498927468 Aug 29 12:55:52 PM UTC 24 Aug 29 12:56:05 PM UTC 24 3850022979 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_volatile_unlock_smoke.1055886497 Aug 29 12:56:03 PM UTC 24 Aug 29 12:56:05 PM UTC 24 45082267 ps
T501 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_sec_token_mux.3614825902 Aug 29 12:55:52 PM UTC 24 Aug 29 12:56:07 PM UTC 24 1657483062 ps
T502 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_smoke.83102993 Aug 29 12:56:03 PM UTC 24 Aug 29 12:56:07 PM UTC 24 34836204 ps
T503 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_prog_failure.2493414298 Aug 29 12:56:04 PM UTC 24 Aug 29 12:56:08 PM UTC 24 84913921 ps
T504 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_jtag_errors.850883505 Aug 29 12:55:20 PM UTC 24 Aug 29 12:56:08 PM UTC 24 9060884862 ps
T505 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_post_trans.2861039815 Aug 29 12:55:56 PM UTC 24 Aug 29 12:56:09 PM UTC 24 693604320 ps
T506 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_errors.631386548 Aug 29 12:55:58 PM UTC 24 Aug 29 12:56:09 PM UTC 24 1483465417 ps
T82 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_smoke.731563892 Aug 29 12:56:09 PM UTC 24 Aug 29 12:56:12 PM UTC 24 19190233 ps
T507 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_state_failure.4035180223 Aug 29 12:55:37 PM UTC 24 Aug 29 12:56:09 PM UTC 24 971802383 ps
T508 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_prog_failure.3492560247 Aug 29 12:55:50 PM UTC 24 Aug 29 12:56:10 PM UTC 24 4088448825 ps
T509 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_alert_test.4184061398 Aug 29 12:56:08 PM UTC 24 Aug 29 12:56:10 PM UTC 24 38889422 ps
T510 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_token_mux.2873988057 Aug 29 12:55:59 PM UTC 24 Aug 29 12:56:10 PM UTC 24 846141627 ps
T511 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_jtag_access.1732216363 Aug 29 12:55:59 PM UTC 24 Aug 29 12:56:11 PM UTC 24 290773565 ps
T512 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_post_trans.2638999091 Aug 29 12:56:03 PM UTC 24 Aug 29 12:56:11 PM UTC 24 464157035 ps
T513 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_volatile_unlock_smoke.3688072321 Aug 29 12:56:09 PM UTC 24 Aug 29 12:56:12 PM UTC 24 14670433 ps
T514 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_errors.3377806396 Aug 29 12:55:32 PM UTC 24 Aug 29 12:56:12 PM UTC 24 9133638953 ps
T515 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_errors.1965069632 Aug 29 12:56:29 PM UTC 24 Aug 29 12:56:49 PM UTC 24 3154422739 ps
T516 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_errors.1925393654 Aug 29 12:56:38 PM UTC 24 Aug 29 12:56:50 PM UTC 24 258470815 ps
T517 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_post_trans.436859302 Aug 29 12:55:50 PM UTC 24 Aug 29 12:56:13 PM UTC 24 910735491 ps
T518 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_sec_mubi.3810323584 Aug 29 12:55:59 PM UTC 24 Aug 29 12:56:13 PM UTC 24 800777421 ps
T519 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_security_escalation.1690303349 Aug 29 12:55:59 PM UTC 24 Aug 29 12:56:14 PM UTC 24 558844533 ps
T520 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_prog_failure.2817378954 Aug 29 12:56:11 PM UTC 24 Aug 29 12:56:15 PM UTC 24 186612233 ps
T521 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_jtag_access.3421399136 Aug 29 12:56:11 PM UTC 24 Aug 29 12:56:16 PM UTC 24 429356626 ps
T522 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_mux.3024705195 Aug 29 12:56:06 PM UTC 24 Aug 29 12:56:16 PM UTC 24 715911319 ps
T523 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_jtag_access.2406400049 Aug 29 12:56:04 PM UTC 24 Aug 29 12:56:16 PM UTC 24 1109184932 ps
T524 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_volatile_unlock_smoke.4244395587 Aug 29 12:56:14 PM UTC 24 Aug 29 12:56:16 PM UTC 24 40713838 ps
T525 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_security_escalation.1408428643 Aug 29 12:56:04 PM UTC 24 Aug 29 12:56:17 PM UTC 24 1665793843 ps
T526 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_mubi.1699410396 Aug 29 12:56:06 PM UTC 24 Aug 29 12:56:17 PM UTC 24 744558654 ps
T527 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_alert_test.582020238 Aug 29 12:56:14 PM UTC 24 Aug 29 12:56:17 PM UTC 24 18164972 ps
T144 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all_with_rand_reset.2227414641 Aug 29 12:54:05 PM UTC 24 Aug 29 12:56:18 PM UTC 24 3885482990 ps
T528 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_failure.2797943239 Aug 29 12:56:21 PM UTC 24 Aug 29 12:56:50 PM UTC 24 325361330 ps
T529 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_smoke.4088005131 Aug 29 12:56:14 PM UTC 24 Aug 29 12:56:19 PM UTC 24 46717051 ps
T530 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_state_failure.2526259931 Aug 29 12:55:40 PM UTC 24 Aug 29 12:56:19 PM UTC 24 9973425933 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/3.lc_ctrl_stress_all.3067746818 Aug 29 12:52:38 PM UTC 24 Aug 29 12:56:20 PM UTC 24 14056402023 ps
T531 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_jtag_state_failure.3062105581 Aug 29 12:55:29 PM UTC 24 Aug 29 12:56:20 PM UTC 24 1584278940 ps
T532 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_prog_failure.1462828962 Aug 29 12:56:16 PM UTC 24 Aug 29 12:56:21 PM UTC 24 102365078 ps
T533 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_jtag_errors.4290249135 Aug 29 12:55:41 PM UTC 24 Aug 29 12:56:22 PM UTC 24 14150787600 ps
T534 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_sec_token_digest.3368943957 Aug 29 12:56:06 PM UTC 24 Aug 29 12:56:22 PM UTC 24 382563370 ps
T535 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_alert_test.2431634614 Aug 29 12:56:19 PM UTC 24 Aug 29 12:56:22 PM UTC 24 16195859 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_post_trans.1431622662 Aug 29 12:56:11 PM UTC 24 Aug 29 12:56:22 PM UTC 24 498017297 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_errors.1420474579 Aug 29 12:56:04 PM UTC 24 Aug 29 12:56:23 PM UTC 24 6404667599 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_mux.2354963579 Aug 29 12:56:11 PM UTC 24 Aug 29 12:56:23 PM UTC 24 1505523742 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_volatile_unlock_smoke.1344063585 Aug 29 12:56:21 PM UTC 24 Aug 29 12:56:24 PM UTC 24 46987353 ps
T83 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_smoke.1407097000 Aug 29 12:56:21 PM UTC 24 Aug 29 12:56:24 PM UTC 24 15516150 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_security_escalation.1094972773 Aug 29 12:56:11 PM UTC 24 Aug 29 12:56:24 PM UTC 24 9632563029 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_state_failure.566125803 Aug 29 12:55:46 PM UTC 24 Aug 29 12:56:25 PM UTC 24 212850675 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_errors.293103274 Aug 29 12:56:11 PM UTC 24 Aug 29 12:56:25 PM UTC 24 327714249 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_prog_failure.2391199564 Aug 29 12:56:23 PM UTC 24 Aug 29 12:56:27 PM UTC 24 26831648 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_jtag_access.914090754 Aug 29 12:56:18 PM UTC 24 Aug 29 12:56:27 PM UTC 24 476330216 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_alert_test.2041897565 Aug 29 12:56:26 PM UTC 24 Aug 29 12:56:28 PM UTC 24 55900943 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_post_trans.179685964 Aug 29 12:56:15 PM UTC 24 Aug 29 12:56:28 PM UTC 24 279871529 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_volatile_unlock_smoke.2542241107 Aug 29 12:56:27 PM UTC 24 Aug 29 12:56:29 PM UTC 24 47102529 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_jtag_access.266688918 Aug 29 12:56:23 PM UTC 24 Aug 29 12:56:29 PM UTC 24 1032936033 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_mux.1204261420 Aug 29 12:56:18 PM UTC 24 Aug 29 12:56:29 PM UTC 24 1195801301 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_state_failure.579364785 Aug 29 12:55:55 PM UTC 24 Aug 29 12:56:30 PM UTC 24 306431935 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_errors.478692384 Aug 29 12:56:16 PM UTC 24 Aug 29 12:56:30 PM UTC 24 426026661 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_security_escalation.1241053941 Aug 29 12:56:18 PM UTC 24 Aug 29 12:56:31 PM UTC 24 1651016343 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_smoke.2326628774 Aug 29 12:56:26 PM UTC 24 Aug 29 12:56:32 PM UTC 24 1097219973 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_token_digest.3318229714 Aug 29 12:56:12 PM UTC 24 Aug 29 12:56:32 PM UTC 24 434847669 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_state_post_trans.1411076485 Aug 29 12:56:21 PM UTC 24 Aug 29 12:56:33 PM UTC 24 182780180 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_prog_failure.4224243773 Aug 29 12:56:29 PM UTC 24 Aug 29 12:56:33 PM UTC 24 170029186 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_alert_test.3299735443 Aug 29 12:56:33 PM UTC 24 Aug 29 12:56:36 PM UTC 24 50573503 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_sec_mubi.531653122 Aug 29 12:56:11 PM UTC 24 Aug 29 12:56:36 PM UTC 24 2150318537 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_mux.3413924855 Aug 29 12:56:24 PM UTC 24 Aug 29 12:56:36 PM UTC 24 609307879 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_volatile_unlock_smoke.2910359902 Aug 29 12:56:34 PM UTC 24 Aug 29 12:56:37 PM UTC 24 20684551 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_smoke.2324834332 Aug 29 12:56:34 PM UTC 24 Aug 29 12:56:37 PM UTC 24 11609323 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_state_failure.3609635830 Aug 29 12:56:03 PM UTC 24 Aug 29 12:56:38 PM UTC 24 300783496 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_post_trans.3933456989 Aug 29 12:56:28 PM UTC 24 Aug 29 12:56:39 PM UTC 24 62081145 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_token_digest.1357852682 Aug 29 12:56:24 PM UTC 24 Aug 29 12:56:39 PM UTC 24 275244623 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_mubi.3135351234 Aug 29 12:56:18 PM UTC 24 Aug 29 12:56:39 PM UTC 24 311731262 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_state_failure.1145021847 Aug 29 12:56:14 PM UTC 24 Aug 29 12:56:41 PM UTC 24 959417971 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/22.lc_ctrl_state_failure.450459542 Aug 29 12:56:11 PM UTC 24 Aug 29 12:56:41 PM UTC 24 741369046 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_security_escalation.1784873294 Aug 29 12:56:30 PM UTC 24 Aug 29 12:56:41 PM UTC 24 1541718286 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_sec_token_digest.2778302114 Aug 29 12:56:18 PM UTC 24 Aug 29 12:56:41 PM UTC 24 666245510 ps
T145 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all_with_rand_reset.2814546515 Aug 29 12:55:35 PM UTC 24 Aug 29 12:56:42 PM UTC 24 2007981332 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_jtag_access.813076043 Aug 29 12:56:30 PM UTC 24 Aug 29 12:56:42 PM UTC 24 515253759 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_prog_failure.1067656856 Aug 29 12:56:38 PM UTC 24 Aug 29 12:56:42 PM UTC 24 45374097 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_post_trans.4168805882 Aug 29 12:56:38 PM UTC 24 Aug 29 12:56:42 PM UTC 24 59200511 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_errors.3846538960 Aug 29 12:56:23 PM UTC 24 Aug 29 12:56:42 PM UTC 24 322269799 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_security_escalation.2479703984 Aug 29 12:56:23 PM UTC 24 Aug 29 12:56:42 PM UTC 24 1009428357 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_alert_test.2442263911 Aug 29 12:56:42 PM UTC 24 Aug 29 12:56:44 PM UTC 24 54400336 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_mux.969517235 Aug 29 12:56:30 PM UTC 24 Aug 29 12:56:44 PM UTC 24 409815409 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_volatile_unlock_smoke.1726282242 Aug 29 12:56:43 PM UTC 24 Aug 29 12:56:46 PM UTC 24 23727833 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_token_digest.1005472766 Aug 29 12:56:32 PM UTC 24 Aug 29 12:56:47 PM UTC 24 247226859 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_smoke.1569564278 Aug 29 12:56:43 PM UTC 24 Aug 29 12:56:47 PM UTC 24 27075281 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_sec_mubi.1398270830 Aug 29 12:56:30 PM UTC 24 Aug 29 12:56:48 PM UTC 24 1185579629 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_prog_failure.5865510 Aug 29 12:56:44 PM UTC 24 Aug 29 12:56:48 PM UTC 24 98531827 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_jtag_access.1498158060 Aug 29 12:56:39 PM UTC 24 Aug 29 12:56:51 PM UTC 24 929597519 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_digest.1310592817 Aug 29 12:56:40 PM UTC 24 Aug 29 12:56:51 PM UTC 24 270437082 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_alert_test.1879130497 Aug 29 12:56:48 PM UTC 24 Aug 29 12:56:51 PM UTC 24 104895000 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_security_escalation.3072588928 Aug 29 12:56:38 PM UTC 24 Aug 29 12:56:51 PM UTC 24 298699728 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_volatile_unlock_smoke.3738239429 Aug 29 12:56:50 PM UTC 24 Aug 29 12:56:52 PM UTC 24 47421277 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_mubi.2431445746 Aug 29 12:56:39 PM UTC 24 Aug 29 12:56:52 PM UTC 24 1019791584 ps
T588 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_sec_mubi.3060202301 Aug 29 12:56:24 PM UTC 24 Aug 29 12:56:52 PM UTC 24 2407434372 ps
T589 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_smoke.1298768457 Aug 29 12:56:49 PM UTC 24 Aug 29 12:56:53 PM UTC 24 69650023 ps
T590 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_sec_token_mux.156532220 Aug 29 12:56:40 PM UTC 24 Aug 29 12:56:54 PM UTC 24 565710388 ps
T591 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_state_failure.4045957752 Aug 29 12:55:50 PM UTC 24 Aug 29 12:56:54 PM UTC 24 6592085725 ps
T592 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_security_escalation.2766674443 Aug 29 12:56:44 PM UTC 24 Aug 29 12:56:54 PM UTC 24 1226690764 ps
T593 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/26.lc_ctrl_state_failure.2031650986 Aug 29 12:56:36 PM UTC 24 Aug 29 12:56:56 PM UTC 24 431007227 ps
T594 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_post_trans.3328995064 Aug 29 12:56:44 PM UTC 24 Aug 29 12:56:56 PM UTC 24 124028672 ps
T595 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_prog_failure.2179395396 Aug 29 12:56:51 PM UTC 24 Aug 29 12:56:56 PM UTC 24 265688777 ps
T596 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_alert_test.427726421 Aug 29 12:56:55 PM UTC 24 Aug 29 12:56:58 PM UTC 24 135120530 ps
T597 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_volatile_unlock_smoke.4203318110 Aug 29 12:56:55 PM UTC 24 Aug 29 12:56:58 PM UTC 24 20166761 ps
T598 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_jtag_access.2104581414 Aug 29 12:56:44 PM UTC 24 Aug 29 12:56:58 PM UTC 24 997852892 ps
T599 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_errors.2286285418 Aug 29 12:56:44 PM UTC 24 Aug 29 12:56:59 PM UTC 24 1338575757 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_post_trans.1665441766 Aug 29 12:57:22 PM UTC 24 Aug 29 12:57:36 PM UTC 24 161546563 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_post_trans.1740796437 Aug 29 12:56:51 PM UTC 24 Aug 29 12:57:00 PM UTC 24 119666282 ps
T602 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_mux.1382802254 Aug 29 12:56:45 PM UTC 24 Aug 29 12:57:00 PM UTC 24 578308784 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_smoke.3181869427 Aug 29 12:56:55 PM UTC 24 Aug 29 12:57:00 PM UTC 24 51764043 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_token_digest.2683387931 Aug 29 12:56:46 PM UTC 24 Aug 29 12:57:02 PM UTC 24 970586306 ps
T605 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_prog_failure.2514285766 Aug 29 12:56:58 PM UTC 24 Aug 29 12:57:03 PM UTC 24 76386294 ps
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