Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.25 97.99 95.77 93.40 100.00 98.55 98.76 96.29


Total test records in report: 999
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html

T606 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_sec_mubi.4104133682 Aug 29 12:56:45 PM UTC 24 Aug 29 12:57:03 PM UTC 24 307020657 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all.3658527487 Aug 29 12:56:32 PM UTC 24 Aug 29 12:57:04 PM UTC 24 791858404 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/16.lc_ctrl_stress_all.1773069945 Aug 29 12:55:25 PM UTC 24 Aug 29 12:57:04 PM UTC 24 4599518579 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_alert_test.2655737697 Aug 29 12:57:03 PM UTC 24 Aug 29 12:57:05 PM UTC 24 41907443 ps
T609 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_volatile_unlock_smoke.281383491 Aug 29 12:57:04 PM UTC 24 Aug 29 12:57:06 PM UTC 24 38545754 ps
T610 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_mux.21275524 Aug 29 12:56:53 PM UTC 24 Aug 29 12:57:07 PM UTC 24 365241976 ps
T611 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_jtag_errors.4027706482 Aug 29 12:55:50 PM UTC 24 Aug 29 12:57:08 PM UTC 24 13868115778 ps
T612 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_post_trans.3259583288 Aug 29 12:56:57 PM UTC 24 Aug 29 12:57:08 PM UTC 24 200091265 ps
T613 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_errors.1071326241 Aug 29 12:56:51 PM UTC 24 Aug 29 12:57:08 PM UTC 24 2978412776 ps
T614 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_security_escalation.1368654995 Aug 29 12:56:53 PM UTC 24 Aug 29 12:57:09 PM UTC 24 984177367 ps
T615 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_smoke.4229884994 Aug 29 12:57:04 PM UTC 24 Aug 29 12:57:09 PM UTC 24 131105849 ps
T616 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_prog_failure.1134601370 Aug 29 12:57:06 PM UTC 24 Aug 29 12:57:10 PM UTC 24 29855004 ps
T617 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_mubi.226016216 Aug 29 12:56:53 PM UTC 24 Aug 29 12:57:10 PM UTC 24 309746396 ps
T618 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_sec_token_digest.2272912049 Aug 29 12:56:53 PM UTC 24 Aug 29 12:57:12 PM UTC 24 443199777 ps
T619 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_security_escalation.1148954300 Aug 29 12:56:59 PM UTC 24 Aug 29 12:57:13 PM UTC 24 3268560148 ps
T620 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_state_failure.4203784667 Aug 29 12:56:28 PM UTC 24 Aug 29 12:57:13 PM UTC 24 723936980 ps
T621 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_alert_test.2369945929 Aug 29 12:57:11 PM UTC 24 Aug 29 12:57:13 PM UTC 24 24750177 ps
T622 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_errors.3549873697 Aug 29 12:56:59 PM UTC 24 Aug 29 12:57:15 PM UTC 24 395480369 ps
T623 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_jtag_access.79828677 Aug 29 12:56:59 PM UTC 24 Aug 29 12:57:16 PM UTC 24 1746780901 ps
T624 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_smoke.186418768 Aug 29 12:57:13 PM UTC 24 Aug 29 12:57:16 PM UTC 24 22579626 ps
T625 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_prog_failure.2783149032 Aug 29 12:58:56 PM UTC 24 Aug 29 12:59:01 PM UTC 24 64696806 ps
T626 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_mubi.2082404135 Aug 29 12:57:00 PM UTC 24 Aug 29 12:57:17 PM UTC 24 432613123 ps
T627 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_post_trans.510529187 Aug 29 12:57:06 PM UTC 24 Aug 29 12:57:17 PM UTC 24 68238086 ps
T628 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_jtag_access.866483834 Aug 29 12:57:09 PM UTC 24 Aug 29 12:57:17 PM UTC 24 200271681 ps
T629 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_volatile_unlock_smoke.2508644315 Aug 29 12:57:15 PM UTC 24 Aug 29 12:57:17 PM UTC 24 36010503 ps
T630 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_mux.1751923517 Aug 29 12:57:00 PM UTC 24 Aug 29 12:57:17 PM UTC 24 1301942215 ps
T631 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/20.lc_ctrl_stress_all.2705224089 Aug 29 12:56:00 PM UTC 24 Aug 29 12:57:18 PM UTC 24 2593561590 ps
T632 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_prog_failure.3598506872 Aug 29 12:57:15 PM UTC 24 Aug 29 12:57:19 PM UTC 24 1007899354 ps
T633 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_mux.2183952849 Aug 29 12:57:09 PM UTC 24 Aug 29 12:57:20 PM UTC 24 2849963339 ps
T634 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/27.lc_ctrl_state_failure.251337564 Aug 29 12:56:44 PM UTC 24 Aug 29 12:57:20 PM UTC 24 334626378 ps
T635 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_alert_test.2653352629 Aug 29 12:57:19 PM UTC 24 Aug 29 12:57:21 PM UTC 24 27506938 ps
T636 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_volatile_unlock_smoke.776878766 Aug 29 12:57:20 PM UTC 24 Aug 29 12:57:22 PM UTC 24 45055416 ps
T637 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_post_trans.1645105082 Aug 29 12:57:15 PM UTC 24 Aug 29 12:57:23 PM UTC 24 144138031 ps
T638 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_jtag_access.2323424084 Aug 29 12:57:26 PM UTC 24 Aug 29 12:57:37 PM UTC 24 1839068791 ps
T639 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_sec_token_digest.3054976738 Aug 29 12:57:02 PM UTC 24 Aug 29 12:57:24 PM UTC 24 1388814301 ps
T640 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/23.lc_ctrl_stress_all.1959147600 Aug 29 12:56:18 PM UTC 24 Aug 29 12:57:25 PM UTC 24 12296827673 ps
T641 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_security_escalation.2762080648 Aug 29 12:57:08 PM UTC 24 Aug 29 12:57:25 PM UTC 24 298305767 ps
T642 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_errors.1831526803 Aug 29 12:57:07 PM UTC 24 Aug 29 12:57:26 PM UTC 24 1539760768 ps
T643 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_security_escalation.523301284 Aug 29 12:57:16 PM UTC 24 Aug 29 12:57:26 PM UTC 24 367892412 ps
T644 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_jtag_access.573561129 Aug 29 12:56:53 PM UTC 24 Aug 29 12:57:26 PM UTC 24 1195977366 ps
T645 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_smoke.1429308843 Aug 29 12:57:20 PM UTC 24 Aug 29 12:57:27 PM UTC 24 60694333 ps
T146 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/19.lc_ctrl_stress_all_with_rand_reset.1688343464 Aug 29 12:55:54 PM UTC 24 Aug 29 12:57:27 PM UTC 24 4185118323 ps
T197 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_prog_failure.637285203 Aug 29 12:57:24 PM UTC 24 Aug 29 12:57:28 PM UTC 24 64527058 ps
T198 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_mux.1662763480 Aug 29 12:57:17 PM UTC 24 Aug 29 12:57:28 PM UTC 24 1230895376 ps
T199 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_errors.2486626873 Aug 29 12:57:16 PM UTC 24 Aug 29 12:57:28 PM UTC 24 1350992794 ps
T200 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_state_failure.3209526433 Aug 29 12:56:51 PM UTC 24 Aug 29 12:57:30 PM UTC 24 905724572 ps
T201 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/24.lc_ctrl_stress_all.4251075688 Aug 29 12:56:24 PM UTC 24 Aug 29 12:57:30 PM UTC 24 1429574373 ps
T202 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_alert_test.2159479167 Aug 29 12:57:29 PM UTC 24 Aug 29 12:57:32 PM UTC 24 82052960 ps
T203 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_volatile_unlock_smoke.927097167 Aug 29 12:57:29 PM UTC 24 Aug 29 12:57:32 PM UTC 24 34744938 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/29.lc_ctrl_state_failure.383911488 Aug 29 12:56:57 PM UTC 24 Aug 29 12:57:33 PM UTC 24 164665536 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_token_digest.3914832230 Aug 29 12:57:11 PM UTC 24 Aug 29 12:57:34 PM UTC 24 571865817 ps
T646 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_security_escalation.3748363352 Aug 29 12:57:25 PM UTC 24 Aug 29 12:57:34 PM UTC 24 183840967 ps
T647 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_smoke.4003706598 Aug 29 12:57:29 PM UTC 24 Aug 29 12:57:35 PM UTC 24 68009919 ps
T648 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_mubi.3356718014 Aug 29 12:57:17 PM UTC 24 Aug 29 12:57:35 PM UTC 24 310200010 ps
T649 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_sec_mubi.1724841833 Aug 29 12:57:09 PM UTC 24 Aug 29 12:57:36 PM UTC 24 606416323 ps
T650 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/8.lc_ctrl_stress_all.1035298119 Aug 29 12:53:51 PM UTC 24 Aug 29 12:57:36 PM UTC 24 9594326997 ps
T651 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_sec_token_digest.249844981 Aug 29 12:57:17 PM UTC 24 Aug 29 12:57:36 PM UTC 24 682524161 ps
T652 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_post_trans.1128859889 Aug 29 12:57:31 PM UTC 24 Aug 29 12:57:37 PM UTC 24 276173810 ps
T653 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_prog_failure.267456970 Aug 29 12:57:31 PM UTC 24 Aug 29 12:57:38 PM UTC 24 432032597 ps
T147 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/7.lc_ctrl_stress_all_with_rand_reset.3982893847 Aug 29 12:53:40 PM UTC 24 Aug 29 12:57:39 PM UTC 24 12174788380 ps
T654 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_jtag_access.2635821755 Aug 29 12:57:16 PM UTC 24 Aug 29 12:57:39 PM UTC 24 3338888277 ps
T655 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_alert_test.2924923581 Aug 29 12:57:37 PM UTC 24 Aug 29 12:57:39 PM UTC 24 110633100 ps
T656 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_volatile_unlock_smoke.1108335204 Aug 29 12:57:37 PM UTC 24 Aug 29 12:57:40 PM UTC 24 19204312 ps
T657 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_mubi.1671588070 Aug 29 12:57:26 PM UTC 24 Aug 29 12:57:41 PM UTC 24 270596389 ps
T658 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_smoke.269630295 Aug 29 12:57:37 PM UTC 24 Aug 29 12:57:42 PM UTC 24 205967165 ps
T659 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_prog_failure.1725545789 Aug 29 12:57:38 PM UTC 24 Aug 29 12:57:43 PM UTC 24 464323405 ps
T660 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_jtag_access.1032596128 Aug 29 12:57:33 PM UTC 24 Aug 29 12:57:44 PM UTC 24 1103752001 ps
T661 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_digest.3682014040 Aug 29 12:57:28 PM UTC 24 Aug 29 12:57:44 PM UTC 24 1649896261 ps
T662 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/30.lc_ctrl_state_failure.2316793981 Aug 29 12:57:04 PM UTC 24 Aug 29 12:57:44 PM UTC 24 577702322 ps
T663 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_errors.3984044705 Aug 29 12:57:32 PM UTC 24 Aug 29 12:57:45 PM UTC 24 441929416 ps
T664 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_digest.3592168267 Aug 29 12:58:02 PM UTC 24 Aug 29 12:58:22 PM UTC 24 549601147 ps
T665 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_sec_token_mux.2860727605 Aug 29 12:57:27 PM UTC 24 Aug 29 12:57:47 PM UTC 24 1534734979 ps
T666 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_alert_test.2289255282 Aug 29 12:57:45 PM UTC 24 Aug 29 12:57:47 PM UTC 24 38459437 ps
T667 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_volatile_unlock_smoke.417560328 Aug 29 12:57:45 PM UTC 24 Aug 29 12:57:48 PM UTC 24 63554629 ps
T668 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_mux.1885291293 Aug 29 12:57:41 PM UTC 24 Aug 29 12:57:48 PM UTC 24 182248429 ps
T669 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_mux.2252944317 Aug 29 12:57:35 PM UTC 24 Aug 29 12:57:49 PM UTC 24 278701842 ps
T670 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_mubi.1640076180 Aug 29 12:57:34 PM UTC 24 Aug 29 12:57:50 PM UTC 24 382217337 ps
T671 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_security_escalation.3211107347 Aug 29 12:57:33 PM UTC 24 Aug 29 12:57:50 PM UTC 24 833217126 ps
T672 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_post_trans.1985996595 Aug 29 12:57:38 PM UTC 24 Aug 29 12:57:50 PM UTC 24 120811069 ps
T673 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_smoke.1817267565 Aug 29 12:57:45 PM UTC 24 Aug 29 12:57:51 PM UTC 24 43480823 ps
T148 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all_with_rand_reset.1583247033 Aug 29 12:55:05 PM UTC 24 Aug 29 12:57:51 PM UTC 24 14357296938 ps
T674 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_prog_failure.600839924 Aug 29 12:57:48 PM UTC 24 Aug 29 12:57:52 PM UTC 24 82767429 ps
T675 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_security_escalation.2995977256 Aug 29 12:57:41 PM UTC 24 Aug 29 12:57:52 PM UTC 24 293509665 ps
T676 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_sec_token_digest.354733197 Aug 29 12:57:35 PM UTC 24 Aug 29 12:57:53 PM UTC 24 481571359 ps
T677 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_jtag_access.1119392242 Aug 29 12:57:49 PM UTC 24 Aug 29 12:57:54 PM UTC 24 197440635 ps
T678 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_alert_test.4197570797 Aug 29 12:57:53 PM UTC 24 Aug 29 12:57:56 PM UTC 24 41473026 ps
T679 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_token_digest.1353248259 Aug 29 12:57:42 PM UTC 24 Aug 29 12:57:56 PM UTC 24 449565864 ps
T680 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_volatile_unlock_smoke.3252004793 Aug 29 12:57:54 PM UTC 24 Aug 29 12:57:56 PM UTC 24 12778346 ps
T681 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_smoke.3724201038 Aug 29 12:57:53 PM UTC 24 Aug 29 12:57:57 PM UTC 24 99414787 ps
T682 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_post_trans.2750032084 Aug 29 12:57:47 PM UTC 24 Aug 29 12:57:57 PM UTC 24 916981442 ps
T683 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_errors.3554689847 Aug 29 12:57:41 PM UTC 24 Aug 29 12:57:58 PM UTC 24 363617702 ps
T684 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_state_failure.2029815156 Aug 29 12:57:15 PM UTC 24 Aug 29 12:58:01 PM UTC 24 1514066393 ps
T685 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_prog_failure.338044746 Aug 29 12:57:56 PM UTC 24 Aug 29 12:58:02 PM UTC 24 98886801 ps
T686 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_sec_mubi.461175722 Aug 29 12:57:41 PM UTC 24 Aug 29 12:58:02 PM UTC 24 360285463 ps
T687 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all.842936433 Aug 29 12:55:14 PM UTC 24 Aug 29 12:58:02 PM UTC 24 18149915572 ps
T688 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_state_failure.1815043028 Aug 29 12:57:21 PM UTC 24 Aug 29 12:58:04 PM UTC 24 761702482 ps
T689 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_jtag_access.2787248148 Aug 29 12:57:58 PM UTC 24 Aug 29 12:58:04 PM UTC 24 222036246 ps
T690 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_errors.3786787290 Aug 29 12:57:49 PM UTC 24 Aug 29 12:58:05 PM UTC 24 807157090 ps
T691 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_post_trans.2354741885 Aug 29 12:57:55 PM UTC 24 Aug 29 12:58:05 PM UTC 24 156608850 ps
T692 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_security_escalation.1097604970 Aug 29 12:57:49 PM UTC 24 Aug 29 12:58:06 PM UTC 24 1722121636 ps
T149 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/25.lc_ctrl_stress_all_with_rand_reset.3567618952 Aug 29 12:56:33 PM UTC 24 Aug 29 12:58:06 PM UTC 24 8077556304 ps
T693 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_alert_test.2140236863 Aug 29 12:58:04 PM UTC 24 Aug 29 12:58:06 PM UTC 24 24870145 ps
T694 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_mubi.1821858020 Aug 29 12:57:50 PM UTC 24 Aug 29 12:58:07 PM UTC 24 1553406937 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/9.lc_ctrl_stress_all.2785618951 Aug 29 12:54:04 PM UTC 24 Aug 29 12:58:07 PM UTC 24 9985844679 ps
T695 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_volatile_unlock_smoke.464993269 Aug 29 12:58:05 PM UTC 24 Aug 29 12:58:08 PM UTC 24 16669295 ps
T696 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/33.lc_ctrl_state_failure.1241838161 Aug 29 12:57:29 PM UTC 24 Aug 29 12:58:08 PM UTC 24 2888279060 ps
T697 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_digest.2748697538 Aug 29 12:57:51 PM UTC 24 Aug 29 12:58:08 PM UTC 24 223095280 ps
T698 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_smoke.1643147860 Aug 29 12:58:05 PM UTC 24 Aug 29 12:58:09 PM UTC 24 270049378 ps
T699 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_jtag_access.4256922602 Aug 29 12:57:41 PM UTC 24 Aug 29 12:58:09 PM UTC 24 21483381367 ps
T700 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_sec_token_mux.1628000401 Aug 29 12:57:51 PM UTC 24 Aug 29 12:58:09 PM UTC 24 503920849 ps
T701 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_state_failure.939826598 Aug 29 12:57:38 PM UTC 24 Aug 29 12:58:10 PM UTC 24 263058306 ps
T702 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_security_escalation.416793904 Aug 29 12:57:58 PM UTC 24 Aug 29 12:58:10 PM UTC 24 349029764 ps
T703 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_prog_failure.3699658878 Aug 29 12:58:06 PM UTC 24 Aug 29 12:58:11 PM UTC 24 172265897 ps
T704 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_token_mux.2304795386 Aug 29 12:57:59 PM UTC 24 Aug 29 12:58:11 PM UTC 24 253711309 ps
T705 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_alert_test.298239111 Aug 29 12:58:10 PM UTC 24 Aug 29 12:58:13 PM UTC 24 21381891 ps
T706 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_sec_mubi.2738395300 Aug 29 12:57:58 PM UTC 24 Aug 29 12:58:13 PM UTC 24 263950425 ps
T707 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_volatile_unlock_smoke.512675019 Aug 29 12:58:10 PM UTC 24 Aug 29 12:58:13 PM UTC 24 15484760 ps
T708 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_state_failure.3805332077 Aug 29 12:57:54 PM UTC 24 Aug 29 12:58:22 PM UTC 24 290154415 ps
T709 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/34.lc_ctrl_stress_all.1369688141 Aug 29 12:57:42 PM UTC 24 Aug 29 12:58:15 PM UTC 24 5855790744 ps
T710 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_post_trans.1453339892 Aug 29 12:58:06 PM UTC 24 Aug 29 12:58:15 PM UTC 24 213665267 ps
T711 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_smoke.3764330109 Aug 29 12:58:10 PM UTC 24 Aug 29 12:58:15 PM UTC 24 135158187 ps
T712 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_prog_failure.901301634 Aug 29 12:58:12 PM UTC 24 Aug 29 12:58:16 PM UTC 24 61333048 ps
T713 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_errors.1874235256 Aug 29 12:57:58 PM UTC 24 Aug 29 12:58:16 PM UTC 24 974782327 ps
T714 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_post_trans.846343990 Aug 29 12:58:12 PM UTC 24 Aug 29 12:58:17 PM UTC 24 253918915 ps
T715 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_jtag_access.1368177379 Aug 29 12:58:14 PM UTC 24 Aug 29 12:58:18 PM UTC 24 672729913 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_stress_all_with_rand_reset.3945810060 Aug 29 12:57:53 PM UTC 24 Aug 29 12:58:18 PM UTC 24 1474795301 ps
T166 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_alert_test.3482553964 Aug 29 12:58:17 PM UTC 24 Aug 29 12:58:19 PM UTC 24 43695273 ps
T167 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/35.lc_ctrl_state_failure.2581455222 Aug 29 12:57:46 PM UTC 24 Aug 29 12:58:19 PM UTC 24 971527506 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_security_escalation.3294984799 Aug 29 12:58:09 PM UTC 24 Aug 29 12:58:19 PM UTC 24 1650952213 ps
T169 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_digest.3956358184 Aug 29 12:58:09 PM UTC 24 Aug 29 12:58:19 PM UTC 24 669111767 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_volatile_unlock_smoke.4079750868 Aug 29 12:58:18 PM UTC 24 Aug 29 12:58:20 PM UTC 24 13282366 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_smoke.3772533594 Aug 29 12:58:18 PM UTC 24 Aug 29 12:58:20 PM UTC 24 21607392 ps
T172 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_token_mux.16843498 Aug 29 12:58:09 PM UTC 24 Aug 29 12:58:21 PM UTC 24 1199841403 ps
T173 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_prog_failure.388429450 Aug 29 12:58:20 PM UTC 24 Aug 29 12:58:23 PM UTC 24 88871766 ps
T174 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_sec_mubi.791214913 Aug 29 12:58:09 PM UTC 24 Aug 29 12:58:22 PM UTC 24 2636427848 ps
T716 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_security_escalation.439031200 Aug 29 12:58:14 PM UTC 24 Aug 29 12:58:24 PM UTC 24 343145448 ps
T717 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_jtag_access.258579046 Aug 29 12:58:09 PM UTC 24 Aug 29 12:58:24 PM UTC 24 1129735787 ps
T718 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_volatile_unlock_smoke.1819413178 Aug 29 12:58:23 PM UTC 24 Aug 29 12:58:26 PM UTC 24 46677859 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_smoke.66283177 Aug 29 12:58:23 PM UTC 24 Aug 29 12:58:26 PM UTC 24 46461785 ps
T719 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_alert_test.1013067527 Aug 29 12:58:23 PM UTC 24 Aug 29 12:58:26 PM UTC 24 19838198 ps
T720 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_errors.1419625128 Aug 29 12:58:13 PM UTC 24 Aug 29 12:58:26 PM UTC 24 625413967 ps
T721 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_prog_failure.4029564204 Aug 29 12:58:25 PM UTC 24 Aug 29 12:58:27 PM UTC 24 76535337 ps
T722 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_post_trans.2504422706 Aug 29 12:58:19 PM UTC 24 Aug 29 12:58:28 PM UTC 24 65077107 ps
T723 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_mux.4014715243 Aug 29 12:58:21 PM UTC 24 Aug 29 12:58:30 PM UTC 24 1212763704 ps
T724 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_smoke.1534345639 Aug 29 12:58:54 PM UTC 24 Aug 29 12:58:58 PM UTC 24 50170108 ps
T725 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_digest.48593255 Aug 29 12:58:16 PM UTC 24 Aug 29 12:58:30 PM UTC 24 475101520 ps
T726 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_errors.789919724 Aug 29 12:58:09 PM UTC 24 Aug 29 12:58:31 PM UTC 24 2394165023 ps
T187 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_stress_all_with_rand_reset.2214463440 Aug 29 12:58:17 PM UTC 24 Aug 29 12:58:31 PM UTC 24 1656360931 ps
T727 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all.1864828851 Aug 29 12:56:54 PM UTC 24 Aug 29 12:58:31 PM UTC 24 4227105856 ps
T728 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_post_trans.2313753434 Aug 29 12:58:25 PM UTC 24 Aug 29 12:58:31 PM UTC 24 148390468 ps
T729 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_alert_test.2086541565 Aug 29 12:58:29 PM UTC 24 Aug 29 12:58:32 PM UTC 24 27200930 ps
T730 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/13.lc_ctrl_stress_all.1058823345 Aug 29 12:54:52 PM UTC 24 Aug 29 12:58:32 PM UTC 24 16646840413 ps
T731 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_mubi.2130435820 Aug 29 12:58:14 PM UTC 24 Aug 29 12:58:32 PM UTC 24 610096118 ps
T732 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_errors.1643285697 Aug 29 12:58:20 PM UTC 24 Aug 29 12:58:32 PM UTC 24 1015152441 ps
T733 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_security_escalation.3995570767 Aug 29 12:58:20 PM UTC 24 Aug 29 12:58:32 PM UTC 24 506269898 ps
T734 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_sec_token_mux.1223505357 Aug 29 12:58:16 PM UTC 24 Aug 29 12:58:33 PM UTC 24 1078160991 ps
T735 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_volatile_unlock_smoke.2671596528 Aug 29 12:58:31 PM UTC 24 Aug 29 12:58:34 PM UTC 24 43558664 ps
T736 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_token_digest.4207000768 Aug 29 12:58:21 PM UTC 24 Aug 29 12:58:35 PM UTC 24 1087439451 ps
T737 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_sec_mubi.123426196 Aug 29 12:58:21 PM UTC 24 Aug 29 12:58:36 PM UTC 24 1161020154 ps
T738 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_security_escalation.1867062608 Aug 29 12:58:26 PM UTC 24 Aug 29 12:58:36 PM UTC 24 958799270 ps
T739 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_state_failure.2641541651 Aug 29 12:58:06 PM UTC 24 Aug 29 12:58:36 PM UTC 24 700629301 ps
T740 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_smoke.4167923046 Aug 29 12:58:31 PM UTC 24 Aug 29 12:58:37 PM UTC 24 83594193 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_alert_test.1593353939 Aug 29 12:58:35 PM UTC 24 Aug 29 12:58:37 PM UTC 24 15476664 ps
T741 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_jtag_access.676357051 Aug 29 12:58:27 PM UTC 24 Aug 29 12:58:38 PM UTC 24 1915320746 ps
T742 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/38.lc_ctrl_state_failure.340973555 Aug 29 12:58:12 PM UTC 24 Aug 29 12:58:38 PM UTC 24 202053128 ps
T743 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_jtag_access.1168028696 Aug 29 12:58:21 PM UTC 24 Aug 29 12:58:39 PM UTC 24 2522962156 ps
T744 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/17.lc_ctrl_stress_all.573876327 Aug 29 12:55:33 PM UTC 24 Aug 29 12:58:39 PM UTC 24 9074438408 ps
T109 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/15.lc_ctrl_stress_all_with_rand_reset.4090737000 Aug 29 12:55:14 PM UTC 24 Aug 29 12:58:39 PM UTC 24 18124594871 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_prog_failure.1684739606 Aug 29 12:58:33 PM UTC 24 Aug 29 12:58:39 PM UTC 24 100881495 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_digest.2091457307 Aug 29 12:58:27 PM UTC 24 Aug 29 12:58:39 PM UTC 24 1294120138 ps
T159 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/32.lc_ctrl_stress_all_with_rand_reset.711472645 Aug 29 12:57:28 PM UTC 24 Aug 29 12:58:39 PM UTC 24 30037164284 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_volatile_unlock_smoke.591996549 Aug 29 12:58:37 PM UTC 24 Aug 29 12:58:40 PM UTC 24 14189087 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_errors.400870084 Aug 29 12:58:25 PM UTC 24 Aug 29 12:58:41 PM UTC 24 1254082928 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/14.lc_ctrl_stress_all.3328281730 Aug 29 12:55:04 PM UTC 24 Aug 29 12:58:41 PM UTC 24 19169689716 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_smoke.387903117 Aug 29 12:58:36 PM UTC 24 Aug 29 12:58:41 PM UTC 24 199025672 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_token_mux.4171082496 Aug 29 12:58:27 PM UTC 24 Aug 29 12:58:42 PM UTC 24 285232989 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_post_trans.139668093 Aug 29 12:58:33 PM UTC 24 Aug 29 12:58:42 PM UTC 24 61756901 ps
T745 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_alert_test.3292903272 Aug 29 12:58:40 PM UTC 24 Aug 29 12:58:42 PM UTC 24 52496570 ps
T746 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_mubi.511527412 Aug 29 12:58:33 PM UTC 24 Aug 29 12:58:43 PM UTC 24 978739556 ps
T747 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/18.lc_ctrl_stress_all.790182719 Aug 29 12:55:44 PM UTC 24 Aug 29 12:58:43 PM UTC 24 4961223212 ps
T748 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_jtag_access.3571300672 Aug 29 12:58:33 PM UTC 24 Aug 29 12:58:44 PM UTC 24 319598714 ps
T749 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_sec_mubi.671437380 Aug 29 12:58:27 PM UTC 24 Aug 29 12:58:44 PM UTC 24 1532848939 ps
T750 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_volatile_unlock_smoke.591950488 Aug 29 12:58:42 PM UTC 24 Aug 29 12:58:44 PM UTC 24 38572917 ps
T751 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_security_escalation.1216332156 Aug 29 12:58:33 PM UTC 24 Aug 29 12:58:45 PM UTC 24 575730540 ps
T752 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/39.lc_ctrl_state_failure.247678427 Aug 29 12:58:19 PM UTC 24 Aug 29 12:58:45 PM UTC 24 150040536 ps
T753 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_security_escalation.387744963 Aug 29 12:58:43 PM UTC 24 Aug 29 12:58:57 PM UTC 24 436827073 ps
T754 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_prog_failure.3070634853 Aug 29 12:58:38 PM UTC 24 Aug 29 12:58:46 PM UTC 24 320767408 ps
T755 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_smoke.1858583680 Aug 29 12:58:42 PM UTC 24 Aug 29 12:58:46 PM UTC 24 89838466 ps
T756 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_digest.3574281653 Aug 29 12:58:35 PM UTC 24 Aug 29 12:58:46 PM UTC 24 1200449493 ps
T757 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/40.lc_ctrl_state_failure.625449418 Aug 29 12:58:23 PM UTC 24 Aug 29 12:58:47 PM UTC 24 360821343 ps
T758 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_mux.3971194560 Aug 29 12:58:40 PM UTC 24 Aug 29 12:59:00 PM UTC 24 3502659398 ps
T759 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_security_escalation.3064716902 Aug 29 12:58:38 PM UTC 24 Aug 29 12:58:47 PM UTC 24 1989967485 ps
T760 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_prog_failure.2844449392 Aug 29 12:58:42 PM UTC 24 Aug 29 12:58:48 PM UTC 24 212510541 ps
T761 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_mubi.325023023 Aug 29 12:58:45 PM UTC 24 Aug 29 12:59:00 PM UTC 24 237993786 ps
T762 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_post_trans.2731884949 Aug 29 12:58:37 PM UTC 24 Aug 29 12:58:49 PM UTC 24 187721026 ps
T763 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_volatile_unlock_smoke.2400123136 Aug 29 12:58:47 PM UTC 24 Aug 29 12:58:49 PM UTC 24 20773689 ps
T764 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_alert_test.2817364522 Aug 29 12:58:47 PM UTC 24 Aug 29 12:58:49 PM UTC 24 64122183 ps
T765 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_smoke.1045260474 Aug 29 12:58:47 PM UTC 24 Aug 29 12:58:49 PM UTC 24 12877292 ps
T766 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_sec_token_mux.2151543338 Aug 29 12:58:33 PM UTC 24 Aug 29 12:58:49 PM UTC 24 607242115 ps
T767 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_jtag_access.3000939158 Aug 29 12:58:40 PM UTC 24 Aug 29 12:58:50 PM UTC 24 1575885150 ps
T768 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_post_trans.578341021 Aug 29 12:58:47 PM UTC 24 Aug 29 12:58:59 PM UTC 24 154474209 ps
T769 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_mubi.4282327534 Aug 29 12:58:40 PM UTC 24 Aug 29 12:58:53 PM UTC 24 329183102 ps
T770 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_sec_token_digest.3524512114 Aug 29 12:58:40 PM UTC 24 Aug 29 12:58:53 PM UTC 24 1439349216 ps
T771 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_errors.1723234876 Aug 29 12:58:33 PM UTC 24 Aug 29 12:58:53 PM UTC 24 1231858748 ps
T772 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_prog_failure.2211291630 Aug 29 12:58:48 PM UTC 24 Aug 29 12:58:54 PM UTC 24 81241761 ps
T773 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_post_trans.2283507077 Aug 29 12:58:42 PM UTC 24 Aug 29 12:58:54 PM UTC 24 321569396 ps
T774 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_errors.3128782540 Aug 29 12:58:38 PM UTC 24 Aug 29 12:58:56 PM UTC 24 428140244 ps
T775 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_mux.3149461700 Aug 29 12:58:45 PM UTC 24 Aug 29 12:58:56 PM UTC 24 336088487 ps
T776 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_jtag_access.2764370485 Aug 29 12:58:45 PM UTC 24 Aug 29 12:58:56 PM UTC 24 343951458 ps
T777 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_alert_test.2666911813 Aug 29 12:58:53 PM UTC 24 Aug 29 12:58:56 PM UTC 24 32513399 ps
T778 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/31.lc_ctrl_stress_all.2019489392 Aug 29 12:57:17 PM UTC 24 Aug 29 12:58:56 PM UTC 24 28903441870 ps
T779 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_volatile_unlock_smoke.3815992525 Aug 29 12:58:54 PM UTC 24 Aug 29 12:58:57 PM UTC 24 13390357 ps
T780 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/36.lc_ctrl_stress_all.273496592 Aug 29 12:58:02 PM UTC 24 Aug 29 12:58:57 PM UTC 24 2785399086 ps
T781 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/42.lc_ctrl_state_failure.2482977987 Aug 29 12:58:37 PM UTC 24 Aug 29 12:58:59 PM UTC 24 875530613 ps
T160 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/28.lc_ctrl_stress_all_with_rand_reset.2865647670 Aug 29 12:56:54 PM UTC 24 Aug 29 12:59:01 PM UTC 24 4404314278 ps
T782 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_alert_test.2422795455 Aug 29 12:58:59 PM UTC 24 Aug 29 12:59:01 PM UTC 24 87296623 ps
T783 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/41.lc_ctrl_state_failure.2051404620 Aug 29 12:58:31 PM UTC 24 Aug 29 12:59:01 PM UTC 24 2337748333 ps
T784 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_jtag_access.398158003 Aug 29 12:58:49 PM UTC 24 Aug 29 12:59:02 PM UTC 24 1318738538 ps
T785 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_errors.3971623804 Aug 29 12:58:43 PM UTC 24 Aug 29 12:59:02 PM UTC 24 1230497023 ps
T786 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_state_failure.838551958 Aug 29 12:58:47 PM UTC 24 Aug 29 12:59:02 PM UTC 24 819416136 ps
T787 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_token_digest.3931001781 Aug 29 12:58:51 PM UTC 24 Aug 29 12:59:02 PM UTC 24 364303470 ps
T788 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_smoke.2949925801 Aug 29 12:59:00 PM UTC 24 Aug 29 12:59:03 PM UTC 24 26912440 ps
T789 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_security_escalation.128351904 Aug 29 12:58:49 PM UTC 24 Aug 29 12:59:03 PM UTC 24 1124649822 ps
T790 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_volatile_unlock_smoke.2584673775 Aug 29 12:59:01 PM UTC 24 Aug 29 12:59:03 PM UTC 24 17406306 ps
T791 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_sec_token_digest.4043193255 Aug 29 12:58:45 PM UTC 24 Aug 29 12:59:04 PM UTC 24 292878991 ps
T792 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_jtag_access.3195498355 Aug 29 12:58:57 PM UTC 24 Aug 29 12:59:05 PM UTC 24 449782213 ps
T793 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_state_post_trans.3662796535 Aug 29 12:59:01 PM UTC 24 Aug 29 12:59:06 PM UTC 24 109194965 ps
T794 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_errors.919990404 Aug 29 12:58:48 PM UTC 24 Aug 29 12:59:07 PM UTC 24 2684983845 ps
T795 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_alert_test.2297079760 Aug 29 12:59:05 PM UTC 24 Aug 29 12:59:07 PM UTC 24 15995076 ps
T796 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_mux.3553034872 Aug 29 12:58:57 PM UTC 24 Aug 29 12:59:07 PM UTC 24 1676963749 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_jtag_access.2281136989 Aug 29 12:59:03 PM UTC 24 Aug 29 12:59:07 PM UTC 24 127429511 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_volatile_unlock_smoke.3409272315 Aug 29 12:59:05 PM UTC 24 Aug 29 12:59:07 PM UTC 24 14447074 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_state_post_trans.2391645047 Aug 29 12:58:54 PM UTC 24 Aug 29 12:59:08 PM UTC 24 197731302 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_smoke.1292874113 Aug 29 12:59:05 PM UTC 24 Aug 29 12:59:09 PM UTC 24 26615416 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_mubi.249385576 Aug 29 12:58:57 PM UTC 24 Aug 29 12:59:09 PM UTC 24 1014711303 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_security_escalation.908192382 Aug 29 12:58:57 PM UTC 24 Aug 29 12:59:10 PM UTC 24 298955740 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_prog_failure.558783837 Aug 29 12:59:01 PM UTC 24 Aug 29 12:59:10 PM UTC 24 535430128 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/44.lc_ctrl_sec_mubi.4214297802 Aug 29 12:58:51 PM UTC 24 Aug 29 12:59:10 PM UTC 24 2797108160 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_sec_token_digest.1616801479 Aug 29 12:58:57 PM UTC 24 Aug 29 12:59:11 PM UTC 24 578647704 ps
T161 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/37.lc_ctrl_stress_all_with_rand_reset.2558265928 Aug 29 12:58:09 PM UTC 24 Aug 29 12:59:11 PM UTC 24 13224179732 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/43.lc_ctrl_state_failure.3868662031 Aug 29 12:58:42 PM UTC 24 Aug 29 12:59:12 PM UTC 24 477209100 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/45.lc_ctrl_errors.2337296970 Aug 29 12:58:57 PM UTC 24 Aug 29 12:59:13 PM UTC 24 1223526515 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_sec_mubi.1566710850 Aug 29 12:59:03 PM UTC 24 Aug 29 12:59:14 PM UTC 24 1071374727 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_prog_failure.290215055 Aug 29 12:59:08 PM UTC 24 Aug 29 12:59:14 PM UTC 24 528246159 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_alert_test.3942174348 Aug 29 12:59:11 PM UTC 24 Aug 29 12:59:14 PM UTC 24 33905599 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_volatile_unlock_smoke.15194003 Aug 29 12:59:13 PM UTC 24 Aug 29 12:59:15 PM UTC 24 14084538 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/46.lc_ctrl_errors.3561903612 Aug 29 12:59:03 PM UTC 24 Aug 29 12:59:16 PM UTC 24 528807414 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/47.lc_ctrl_state_post_trans.945118803 Aug 29 12:59:07 PM UTC 24 Aug 29 12:59:17 PM UTC 24 281752449 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/48.lc_ctrl_smoke.2822772276 Aug 29 12:59:11 PM UTC 24 Aug 29 12:59:17 PM UTC 24 78930325 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_28/lc_ctrl_volatile_unlock_enabled-sim-vcs/coverage/default/21.lc_ctrl_stress_all.621854695 Aug 29 12:56:06 PM UTC 24 Aug 29 12:59:40 PM UTC 24 19171408926 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%