Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	852771	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1039785

1

T1

13

T2

216

T3

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1603232	1			T1	20		T2	180		T3	2
values[0x0]	144177	1			T1	5		T2	92		T4	45
values[0x1]	145147	1			T1	11		T2	78		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	675052	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1217504

1

T1

20

T2

249

T3

2

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5218	1			T2	2		T8	4		T14	3
valid_sources[0x01]	4962	1			T2	3		T4	10		T8	1
valid_sources[0x02]	5023	1			T7	1		T8	1		T14	5
valid_sources[0x03]	5208	1			T14	4		T15	9		T31	1
valid_sources[0x04]	5265	1			T5	8		T14	1		T15	5
valid_sources[0x05]	5636	1			T4	1		T5	1		T14	4
valid_sources[0x06]	5360	1			T8	1		T14	9		T15	15
valid_sources[0x07]	5399	1			T1	2		T4	4		T14	2
valid_sources[0x08]	6672	1			T5	1		T14	3		T15	3
valid_sources[0x09]	6283	1			T8	2		T14	2		T15	1
valid_sources[0x0a]	4914	1			T2	16		T4	2		T14	7
valid_sources[0x0b]	5166	1			T5	5		T8	2		T14	2
valid_sources[0x0c]	6127	1			T4	1		T5	7		T14	8
valid_sources[0x0d]	5137	1			T2	1		T4	1		T8	3
valid_sources[0x0e]	5376	1			T1	1		T4	2		T14	1
valid_sources[0x0f]	5277	1			T8	2		T14	2		T15	16
valid_sources[0x10]	5151	1			T4	2		T14	2		T15	3
valid_sources[0x11]	6309	1			T7	5		T14	5		T15	7
valid_sources[0x12]	5009	1			T2	2		T4	2		T5	8
valid_sources[0x13]	5101	1			T14	1		T15	5		T31	4
valid_sources[0x14]	18654	1			T4	4		T14	4		T15	7
valid_sources[0x15]	5160	1			T14	5		T15	13		T31	2
valid_sources[0x16]	5218	1			T2	4		T4	1		T14	5
valid_sources[0x17]	6431	1			T4	1		T5	2		T15	1
valid_sources[0x18]	5385	1			T14	3		T15	1		T45	3
valid_sources[0x19]	5502	1			T4	2		T14	4		T15	2
valid_sources[0x1a]	7164	1			T5	1		T14	5		T15	6
valid_sources[0x1b]	5035	1			T4	3		T8	5		T14	3
valid_sources[0x1c]	5248	1			T1	1		T2	1		T4	1
valid_sources[0x1d]	20060	1			T5	1		T8	1		T14	5
valid_sources[0x1e]	5366	1			T4	2		T8	6		T14	4
valid_sources[0x1f]	10302	1			T14	6		T15	5		T23	1
valid_sources[0x20]	5840	1			T3	1		T4	2		T5	1
valid_sources[0x21]	7296	1			T2	7		T7	3		T14	7
valid_sources[0x22]	5258	1			T4	2		T8	3		T14	11
valid_sources[0x23]	20316	1			T4	1		T14	7		T15	4
valid_sources[0x24]	5150	1			T8	1		T14	4		T15	7
valid_sources[0x25]	6293	1			T2	3		T14	4		T15	21
valid_sources[0x26]	5300	1			T1	1		T14	1		T15	5
valid_sources[0x27]	4844	1			T14	8		T15	3		T45	9
valid_sources[0x28]	9628	1			T5	1		T13	17		T14	5
valid_sources[0x29]	24113	1			T1	6		T14	4		T15	7
valid_sources[0x2a]	5148	1			T5	2		T8	5		T14	4
valid_sources[0x2b]	6740	1			T5	4		T8	3		T14	7
valid_sources[0x2c]	5310	1			T2	10		T3	1		T14	1
valid_sources[0x2d]	11018	1			T5	4		T7	2		T8	1
valid_sources[0x2e]	5166	1			T2	4		T8	2		T15	4
valid_sources[0x2f]	5254	1			T5	2		T14	10		T15	1
valid_sources[0x30]	5487	1			T2	1		T4	2		T14	3
valid_sources[0x31]	5846	1			T4	1		T14	6		T15	5
valid_sources[0x32]	5116	1			T2	2		T8	4		T14	5
valid_sources[0x33]	4962	1			T2	2		T14	4		T15	5
valid_sources[0x34]	6512	1			T2	1		T4	2		T5	2
valid_sources[0x35]	8778	1			T14	5		T15	8		T45	3
valid_sources[0x36]	5430	1			T4	1		T14	10		T15	3
valid_sources[0x37]	4976	1			T2	2		T4	5		T8	2
valid_sources[0x38]	5713	1			T5	4		T14	9		T15	11
valid_sources[0x39]	5068	1			T8	1		T14	5		T15	10
valid_sources[0x3a]	9520	1			T1	2		T7	15		T14	3
valid_sources[0x3b]	5048	1			T4	3		T5	1		T14	3
valid_sources[0x3c]	7701	1			T2	3		T5	3		T14	4
valid_sources[0x3d]	5129	1			T4	1		T7	2		T8	1
valid_sources[0x3e]	5250	1			T2	7		T4	4		T8	1
valid_sources[0x3f]	6470	1			T5	1		T14	3		T15	6
valid_sources[0x40]	5246	1			T2	11		T4	1		T5	2
valid_sources[0x41]	5322	1			T14	3		T15	3		T45	3
valid_sources[0x42]	5240	1			T4	2		T5	3		T14	2
valid_sources[0x43]	6940	1			T4	2		T5	2		T14	5
valid_sources[0x44]	6384	1			T2	2		T4	2		T7	14
valid_sources[0x45]	5441	1			T2	2		T4	3		T14	3
valid_sources[0x46]	5312	1			T4	2		T8	2		T14	5
valid_sources[0x47]	5215	1			T4	1		T14	6		T15	2
valid_sources[0x48]	5391	1			T8	1		T14	5		T31	1
valid_sources[0x49]	5112	1			T2	7		T4	2		T14	2
valid_sources[0x4a]	5176	1			T14	2		T15	4		T31	3
valid_sources[0x4b]	5829	1			T8	1		T14	5		T15	10
valid_sources[0x4c]	5253	1			T4	1		T5	1		T14	4
valid_sources[0x4d]	5287	1			T8	1		T14	5		T15	5
valid_sources[0x4e]	5570	1			T2	2		T14	5		T15	6
valid_sources[0x4f]	5387	1			T4	1		T5	1		T8	2
valid_sources[0x50]	5184	1			T1	3		T4	1		T8	1
valid_sources[0x51]	5314	1			T4	4		T14	7		T15	7
valid_sources[0x52]	5126	1			T2	2		T4	2		T5	5
valid_sources[0x53]	5130	1			T2	2		T14	3		T15	8
valid_sources[0x54]	5857	1			T5	5		T14	2		T23	1
valid_sources[0x55]	6173	1			T2	1		T4	2		T14	3
valid_sources[0x56]	13995	1			T2	9		T5	3		T13	2091
valid_sources[0x57]	6244	1			T2	6		T4	1		T8	1
valid_sources[0x58]	4984	1			T2	3		T8	2		T14	4
valid_sources[0x59]	5218	1			T2	4		T4	1		T5	1
valid_sources[0x5a]	5824	1			T4	1		T5	4		T14	3
valid_sources[0x5b]	5429	1			T5	1		T14	1		T15	4
valid_sources[0x5c]	5835	1			T4	2		T7	3		T8	2
valid_sources[0x5d]	5933	1			T5	4		T14	3		T15	6
valid_sources[0x5e]	7719	1			T2	2		T4	2		T5	9
valid_sources[0x5f]	5948	1			T5	6		T8	2		T14	2
valid_sources[0x60]	6688	1			T4	4		T5	2		T14	7
valid_sources[0x61]	18657	1			T4	3		T14	7		T15	8
valid_sources[0x62]	5174	1			T5	2		T14	6		T15	6
valid_sources[0x63]	4976	1			T2	7		T4	1		T8	1
valid_sources[0x64]	5262	1			T5	3		T14	6		T15	2
valid_sources[0x65]	8376	1			T4	3		T5	1		T14	6
valid_sources[0x66]	5036	1			T4	10		T5	1		T14	8
valid_sources[0x67]	21477	1			T2	3		T7	8		T8	5
valid_sources[0x68]	5332	1			T2	1		T14	3		T15	6
valid_sources[0x69]	5152	1			T5	1		T8	3		T14	4
valid_sources[0x6a]	6489	1			T5	1		T14	1		T31	2
valid_sources[0x6b]	5202	1			T2	3		T4	2		T14	8
valid_sources[0x6c]	5102	1			T14	5		T15	5		T31	3
valid_sources[0x6d]	7664	1			T1	1		T4	1		T5	1
valid_sources[0x6e]	5827	1			T4	1		T5	1		T14	4
valid_sources[0x6f]	5322	1			T2	3		T13	17		T8	1
valid_sources[0x70]	10739	1			T5	3		T14	3		T15	10
valid_sources[0x71]	5343	1			T4	2		T14	2		T15	4
valid_sources[0x72]	6564	1			T4	1		T14	4		T15	4
valid_sources[0x73]	6937	1			T8	5		T14	4		T15	5
valid_sources[0x74]	5022	1			T14	5		T15	1		T31	4
valid_sources[0x75]	5206	1			T7	1		T14	2		T15	9
valid_sources[0x76]	5091	1			T2	7		T8	2		T15	11
valid_sources[0x77]	5303	1			T7	1		T14	5		T15	5
valid_sources[0x78]	5078	1			T4	3		T5	2		T14	2
valid_sources[0x79]	7729	1			T1	2		T2	8		T5	1
valid_sources[0x7a]	5520	1			T14	3		T15	6		T45	8
valid_sources[0x7b]	5159	1			T8	3		T14	7		T15	2
valid_sources[0x7c]	6264	1			T7	7		T14	9		T15	3
valid_sources[0x7d]	5424	1			T14	4		T15	12		T31	2
valid_sources[0x7e]	6244	1			T2	1		T5	1		T7	2
valid_sources[0x7f]	5238	1			T3	1		T5	2		T14	7
valid_sources[0x80]	5322	1			T2	6		T4	1		T14	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

790260

1

T2

77

T3

1

T4

65

values[0x0]

all_enables

biggest_size

125129

1

T1

3

T2

78

T4

33

values[0x1]

all_enables

biggest_size

124396

1

T1

10

T2

61

T3

1