Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	62303667	15868	0	0
claim_transition_if_regwen_rd_A	62303667	1483	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62303667	15868	0	0
T24	42927	0	0	0
T50	179253	0	0	0
T94	204083	1	0	0
T95	0	3	0	0
T96	0	22	0	0
T100	11550	0	0	0
T109	0	16	0	0
T147	0	32	0	0
T148	0	2	0	0
T149	0	3	0	0
T150	0	2	0	0
T151	0	7	0	0
T152	0	2	0	0
T153	39762	0	0	0
T154	138317	0	0	0
T155	1862	0	0	0
T156	2220	0	0	0
T157	4009	0	0	0
T158	33065	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62303667	1483	0	0
T95	374697	4	0	0
T99	413701	0	0	0
T106	0	6	0	0
T114	0	44	0	0
T142	0	4	0	0
T149	0	7	0	0
T152	0	10	0	0
T159	0	5	0	0
T160	0	7	0	0
T161	0	15	0	0
T162	0	447	0	0
T163	16609	0	0	0
T164	2462	0	0	0
T165	36733	0	0	0
T166	37371	0	0	0
T167	30221	0	0	0
T168	33950	0	0	0
T169	16140	0	0	0
T170	12165	0	0	0