Unified Coverage Report :: Module :: prim_generic_clock_mux2

Module : prim_generic_clock_mux2

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.64	100.00	55.56	75.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic	75.00			75.00
tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic	75.00			75.00
tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00
tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic	85.19	100.00	55.56				100.00

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
75.00			75.00				gen_scan.i_dft_tck_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00			75.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
75.00			75.00				u_rst_mux

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_clock_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.19	100.00	55.56				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_prim_rst_n_mux2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_generic_clock_mux2

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Toggle Coverage for Module : prim_generic_clock_mux2

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	8	6	75.00
Total Bits 0->1	4	3	75.00
Total Bits 1->0	4	3	75.00

Ports	4	3	75.00
Port Bits	8	6	75.00
Port Bits 0->1	4	3	75.00
Port Bits 1->0	4	3	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk0_i	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	INPUT
clk1_i	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	INPUT
sel_i	No	No		No		INPUT
clk_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT

---

Assert Coverage for Module : prim_generic_clock_mux2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	45267561	45265929	0	0
selKnown1	60276962	60275330	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	45267561	45265929	0	0
T2	20	19	0	0
T3	1	0	0	0
T4	13	12	0	0
T5	12	11	0	0
T6	48511	48509	0	0
T7	15173	15171	0	0
T8	36337	36335	0	0
T9	0	58322	0	0
T11	30453	30451	0	0
T12	0	121645	0	0
T13	6	5	0	0
T14	69	67	0	0
T15	1	90	0	0
T16	1	60	0	0
T17	1	73	0	0
T18	0	50558	0	0
T19	0	22974	0	0
T20	0	18010	0	0
T21	0	194037	0	0
T22	1	0	0	0
T23	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	60276962	60275330	0	0
T1	1158	1157	0	0
T2	5153	5152	0	0
T3	1008	1007	0	0
T4	5655	5654	0	0
T5	5201	5200	0	0
T6	32478	32477	0	0
T7	14450	14448	0	0
T8	26914	26912	0	0
T9	0	3	0	0
T10	0	1	0	0
T11	22790	22788	0	0
T13	23707	23706	0	0
T14	1	0	0	0
T15	1	0	0	0
T16	1	0	0	0
T17	1	0	0	0
T22	1	0	0	0
T23	1	0	0	0
T24	0	3	0	0
T25	0	2	0	0
T26	0	3	0	0
T27	0	2	0	0
T28	0	5	0	0
T29	0	1	0	0
T30	0	6	0	0
T31	1	0	0	0

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap.i_tck_inv.gen_generic.u_impl_generic.gen_scan.i_dft_tck_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	8	6	75.00
Total Bits 0->1	4	3	75.00
Total Bits 1->0	4	3	75.00

Ports	4	3	75.00
Port Bits	8	6	75.00
Port Bits 0->1	4	3	75.00
Port Bits 1->0	4	3	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk0_i	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	INPUT
clk1_i	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	INPUT
sel_i	No	No		No		INPUT
clk_o	Yes	Yes	T6,T7,T8	Yes	T6,T7,T8	OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_rst_mux.gen_generic.u_impl_generic

	Total	Covered	Percent
Totals	4	3	75.00
Total Bits	8	6	75.00
Total Bits 0->1	4	3	75.00
Total Bits 1->0	4	3	75.00

Ports	4	3	75.00
Port Bits	8	6	75.00
Port Bits 0->1	4	3	75.00
Port Bits 1->0	4	3	75.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk0_i	Yes	Yes	T6,T11,T12	Yes	T6,T7,T8	INPUT
clk1_i	Yes	Yes	T7,T9,T10	Yes	T7,T9,T10	INPUT
sel_i	No	No		No		INPUT
clk_o	Yes	Yes	T6,T11,T12	Yes	T6,T7,T8	OUTPUT

Line Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T6,T7,T8
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T6,T7,T8
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_clock_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	45224758	45223942	0	0
selKnown1	60276042	60275226	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	45224758	45223942	0	0
T6	48497	48496	0	0
T7	15172	15171	0	0
T8	36336	36335	0	0
T9	0	58322	0	0
T11	30443	30442	0	0
T12	0	121645	0	0
T14	1	0	0	0
T15	1	0	0	0
T16	1	0	0	0
T17	1	0	0	0
T18	0	50558	0	0
T19	0	22974	0	0
T20	0	18010	0	0
T21	0	194037	0	0
T22	1	0	0	0
T23	1	0	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	60276042	60275226	0	0
T1	1158	1157	0	0
T2	5153	5152	0	0
T3	1008	1007	0	0
T4	5655	5654	0	0
T5	5201	5200	0	0
T6	32478	32477	0	0
T7	14448	14447	0	0
T8	26913	26912	0	0
T11	22789	22788	0	0
T13	23707	23706	0	0

Line Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
CONT_ASSIGN	17	1	1	100.00

16                        // We model the mux with logic operations for GTECH runs.
17         1/1            assign clk_o = (sel_i & clk1_i) | (~sel_i & clk0_i);
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Covered	Percent
Conditions	9	5	55.56
Logical	9	5	55.56
Non-Logical	0	0
Event	0	0

 LINE       17
 EXPRESSION ((sel_i & clk1_i) | (((~sel_i)) & clk0_i))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Not Covered

 LINE       17
 SUB-EXPRESSION (sel_i & clk1_i)
                 --1--   ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       17
 SUB-EXPRESSION (((~sel_i)) & clk0_i)
                 -----1----   ---2--

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_prim_rst_n_mux2.gen_generic.u_impl_generic

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
selKnown0	42803	41987	0	0
selKnown1	920	104	0	0

selKnown0

Name	Attempts	Real Successes	Failures	Incomplete
Total	42803	41987	0	0
T2	20	19	0	0
T3	1	0	0	0
T4	13	12	0	0
T5	12	11	0	0
T6	14	13	0	0
T7	1	0	0	0
T8	1	0	0	0
T11	10	9	0	0
T13	6	5	0	0
T14	68	67	0	0
T15	0	90	0	0
T16	0	60	0	0
T17	0	73	0	0

selKnown1

Name	Attempts	Real Successes	Failures	Incomplete
Total	920	104	0	0
T7	2	1	0	0
T8	1	0	0	0
T9	0	3	0	0
T10	0	1	0	0
T11	1	0	0	0
T14	1	0	0	0
T15	1	0	0	0
T16	1	0	0	0
T17	1	0	0	0
T22	1	0	0	0
T23	1	0	0	0
T24	0	3	0	0
T25	0	2	0	0
T26	0	3	0	0
T27	0	2	0	0
T28	0	5	0	0
T29	0	1	0	0
T30	0	6	0	0
T31	1	0	0	0