Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	979014	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1166361

1

T1

12

T2

76

T3

21

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1852074	1			T1	5		T2	89		T3	25
values[0x0]	146264	1			T1	4		T2	20		T3	1
values[0x1]	147037	1			T1	11		T2	25		T3	7

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	774915	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1370460

1

T1

15

T2

88

T3

23

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	8362	1			T16	6		T21	1		T40	12
valid_sources[0x01]	7465	1			T14	7		T16	6		T40	16
valid_sources[0x02]	8171	1			T16	9		T21	1		T22	2
valid_sources[0x03]	6843	1			T13	3		T16	6		T40	19
valid_sources[0x04]	7075	1			T13	1		T16	8		T40	15
valid_sources[0x05]	6663	1			T14	6		T16	7		T40	21
valid_sources[0x06]	6961	1			T14	9		T16	5		T40	22
valid_sources[0x07]	61981	1			T14	12		T16	4		T40	21
valid_sources[0x08]	7016	1			T13	2		T14	14		T16	3
valid_sources[0x09]	6881	1			T13	2		T14	2		T6	4
valid_sources[0x0a]	9445	1			T13	2		T14	15		T6	6
valid_sources[0x0b]	7047	1			T13	4		T14	5		T16	3
valid_sources[0x0c]	6557	1			T13	3		T14	1		T16	4
valid_sources[0x0d]	8006	1			T14	5		T16	4		T40	11
valid_sources[0x0e]	8454	1			T13	3		T16	7		T40	14
valid_sources[0x0f]	7008	1			T13	1		T16	7		T21	1
valid_sources[0x10]	6979	1			T13	1		T6	1		T16	5
valid_sources[0x11]	7128	1			T4	17		T13	2		T16	2
valid_sources[0x12]	6843	1			T13	1		T15	100		T16	5
valid_sources[0x13]	7673	1			T14	10		T16	1		T40	13
valid_sources[0x14]	7179	1			T6	5		T16	4		T40	18
valid_sources[0x15]	8185	1			T13	1		T14	7		T6	3
valid_sources[0x16]	7010	1			T13	4		T16	3		T40	28
valid_sources[0x17]	6675	1			T13	5		T14	8		T16	6
valid_sources[0x18]	22644	1			T16	5		T22	3		T31	20
valid_sources[0x19]	6745	1			T13	2		T14	3		T16	7
valid_sources[0x1a]	6876	1			T13	3		T14	1		T16	4
valid_sources[0x1b]	6992	1			T14	5		T16	4		T21	1
valid_sources[0x1c]	6990	1			T13	2		T16	5		T40	15
valid_sources[0x1d]	16359	1			T13	1		T14	3		T16	5
valid_sources[0x1e]	7576	1			T13	3		T14	2		T16	7
valid_sources[0x1f]	6846	1			T14	3		T16	5		T40	20
valid_sources[0x20]	6772	1			T16	2		T40	13		T43	4
valid_sources[0x21]	6922	1			T14	2		T16	5		T22	24
valid_sources[0x22]	6884	1			T14	6		T16	5		T40	16
valid_sources[0x23]	6925	1			T13	2		T14	2		T16	4
valid_sources[0x24]	6741	1			T13	1		T14	24		T16	6
valid_sources[0x25]	7413	1			T13	2		T14	7		T6	1
valid_sources[0x26]	7806	1			T16	3		T21	1		T40	19
valid_sources[0x27]	7392	1			T13	1		T6	2		T16	6
valid_sources[0x28]	7028	1			T12	3		T13	2		T14	10
valid_sources[0x29]	6884	1			T13	3		T16	10		T21	1
valid_sources[0x2a]	6980	1			T13	4		T14	1		T16	9
valid_sources[0x2b]	6629	1			T13	2		T14	4		T15	25
valid_sources[0x2c]	8090	1			T13	1		T14	1		T6	1
valid_sources[0x2d]	7669	1			T13	1		T14	1		T6	11
valid_sources[0x2e]	6774	1			T13	1		T16	6		T40	16
valid_sources[0x2f]	12136	1			T13	2		T14	1		T16	6
valid_sources[0x30]	7305	1			T14	14		T16	5		T40	12
valid_sources[0x31]	7578	1			T13	4		T14	12		T15	2
valid_sources[0x32]	31778	1			T14	13		T16	6		T40	15
valid_sources[0x33]	7712	1			T13	3		T16	7		T40	18
valid_sources[0x34]	11949	1			T13	1		T14	5		T16	8
valid_sources[0x35]	10224	1			T13	3		T16	6		T21	2
valid_sources[0x36]	11240	1			T4	4320		T13	1		T14	5
valid_sources[0x37]	6843	1			T13	3		T14	5		T6	8
valid_sources[0x38]	7348	1			T1	1		T13	1		T16	8
valid_sources[0x39]	11176	1			T13	3		T14	1		T16	6
valid_sources[0x3a]	6507	1			T1	1		T13	1		T14	2
valid_sources[0x3b]	7005	1			T13	3		T16	3		T40	22
valid_sources[0x3c]	6857	1			T13	2		T14	6		T16	3
valid_sources[0x3d]	6881	1			T1	1		T13	2		T15	52
valid_sources[0x3e]	8276	1			T6	5		T16	6		T40	15
valid_sources[0x3f]	7369	1			T13	4		T6	14		T16	2
valid_sources[0x40]	6902	1			T13	1		T14	17		T6	33
valid_sources[0x41]	7024	1			T13	1		T16	3		T21	1
valid_sources[0x42]	6974	1			T13	4		T16	9		T40	14
valid_sources[0x43]	7247	1			T4	17		T13	2		T14	5
valid_sources[0x44]	6733	1			T14	1		T6	15		T16	8
valid_sources[0x45]	11750	1			T13	1		T16	8		T21	1
valid_sources[0x46]	7750	1			T13	3		T14	2		T16	4
valid_sources[0x47]	6856	1			T13	2		T14	8		T16	3
valid_sources[0x48]	8362	1			T16	2		T22	2		T40	19
valid_sources[0x49]	8182	1			T14	10		T15	74		T16	8
valid_sources[0x4a]	9946	1			T13	1		T14	17		T16	6
valid_sources[0x4b]	8437	1			T1	1		T14	10		T16	6
valid_sources[0x4c]	9210	1			T14	1		T16	5		T40	14
valid_sources[0x4d]	6750	1			T3	33		T16	4		T21	1
valid_sources[0x4e]	6704	1			T1	1		T13	3		T14	1
valid_sources[0x4f]	6969	1			T16	2		T40	14		T38	10
valid_sources[0x50]	7974	1			T13	2		T14	8		T16	10
valid_sources[0x51]	6996	1			T13	3		T16	4		T40	12
valid_sources[0x52]	6929	1			T13	1		T16	3		T40	13
valid_sources[0x53]	7001	1			T14	3		T6	5		T16	4
valid_sources[0x54]	6671	1			T13	3		T14	3		T16	8
valid_sources[0x55]	6866	1			T13	1		T14	2		T6	2
valid_sources[0x56]	6832	1			T13	5		T14	6		T16	1
valid_sources[0x57]	10018	1			T14	8		T16	6		T40	17
valid_sources[0x58]	6670	1			T13	4		T14	3		T16	3
valid_sources[0x59]	7118	1			T13	2		T14	5		T16	9
valid_sources[0x5a]	8919	1			T13	4		T16	7		T40	15
valid_sources[0x5b]	7906	1			T14	6		T15	21		T16	6
valid_sources[0x5c]	8430	1			T13	3		T6	3		T15	70
valid_sources[0x5d]	6834	1			T13	5		T15	3		T16	7
valid_sources[0x5e]	6923	1			T13	1		T14	16		T16	8
valid_sources[0x5f]	7017	1			T13	2		T14	9		T16	5
valid_sources[0x60]	7345	1			T14	2		T6	1		T16	4
valid_sources[0x61]	6826	1			T13	1		T14	2		T16	5
valid_sources[0x62]	8667	1			T13	3		T14	2		T6	1
valid_sources[0x63]	6706	1			T13	4		T14	12		T16	4
valid_sources[0x64]	7089	1			T13	2		T14	4		T6	7
valid_sources[0x65]	31319	1			T13	1		T6	13		T16	3
valid_sources[0x66]	8062	1			T1	1		T13	4		T14	15
valid_sources[0x67]	9887	1			T13	6		T14	2		T16	8
valid_sources[0x68]	6623	1			T13	2		T16	3		T40	15
valid_sources[0x69]	7548	1			T13	1		T14	9		T16	10
valid_sources[0x6a]	13190	1			T14	3		T15	13		T16	6
valid_sources[0x6b]	7000	1			T13	2		T14	5		T16	8
valid_sources[0x6c]	7372	1			T1	1		T13	1		T14	5
valid_sources[0x6d]	8162	1			T14	1		T6	1		T16	8
valid_sources[0x6e]	6675	1			T13	5		T6	4		T16	6
valid_sources[0x6f]	7324	1			T14	2		T16	7		T40	16
valid_sources[0x70]	7351	1			T13	1		T16	4		T40	16
valid_sources[0x71]	7993	1			T13	1		T14	11		T16	11
valid_sources[0x72]	7123	1			T13	4		T14	11		T16	2
valid_sources[0x73]	7196	1			T13	1		T14	3		T6	3
valid_sources[0x74]	7656	1			T13	1		T14	6		T16	8
valid_sources[0x75]	6983	1			T13	6		T14	5		T15	10
valid_sources[0x76]	7256	1			T14	3		T6	1		T16	5
valid_sources[0x77]	9894	1			T13	3		T6	2		T16	12
valid_sources[0x78]	9399	1			T13	1		T15	11		T16	6
valid_sources[0x79]	11797	1			T13	1		T14	3		T6	4
valid_sources[0x7a]	7030	1			T16	6		T40	18		T38	7
valid_sources[0x7b]	7300	1			T14	1		T6	1		T16	7
valid_sources[0x7c]	6937	1			T13	2		T14	8		T15	35
valid_sources[0x7d]	10921	1			T13	3		T16	7		T40	20
valid_sources[0x7e]	7008	1			T14	5		T6	35		T16	9
valid_sources[0x7f]	7063	1			T13	2		T14	5		T6	1
valid_sources[0x80]	6650	1			T13	3		T16	7		T21	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

914618

1

T2

42

T3

15

T12

1

values[0x0]

all_enables

biggest_size

126436

1

T1

3

T2

15

T3

1

values[0x1]

all_enables

biggest_size

125307

1

T1

9

T2

19

T3

5