Unified Coverage Report :: Module :: prim_secded_inv_64_57_dec

Module : prim_secded_inv_64_57_dec

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_prim_secded_0.1/rtl/prim_secded_inv_64_57_dec.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_tap_tlul_host.u_rsp_chk.u_chk	15.09			15.09
tb.dut.u_reg_tap.u_chk.u_chk	34.48			34.48
tb.dut.u_reg.u_chk.u_chk	100.00			100.00

---

Module Instance : tb.dut.u_tap_tlul_host.u_rsp_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
15.09			15.09

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
15.09			15.09

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	u_rsp_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg_tap.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
34.48			34.48

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
34.48			34.48

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_reg.u_chk.u_chk

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00					100.00	u_chk

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_secded_inv_64_57_dec

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	232	232	100.00
Total Bits 0->1	116	116	100.00
Total Bits 1->0	116	116	100.00

Ports	4	4	100.00
Port Bits	232	232	100.00
Port Bits 0->1	116	116	100.00
Port Bits 1->0	116	116	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T2,*T3,*T12	Yes	T2,T3,T4	INPUT
data_i[56:43]	Unreachable	Unreachable		Unreachable		INPUT
data_i[63:57]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[56:0]	Yes	Yes	T2,T3,T12	Yes	T2,T3,T4	OUTPUT
syndrome_o[6:0]	Yes	Yes	T6,T7,T11	Yes	T6,T7,T11	OUTPUT
err_o[1:0]	Yes	Yes	T6,T7,T11	Yes	T6,T7,T11	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_tap_tlul_host.u_rsp_chk.u_chk

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	106	16	15.09
Total Bits 0->1	53	8	15.09
Total Bits 1->0	53	8	15.09

Ports	2	0	0.00
Port Bits	106	16	15.09
Port Bits 0->1	53	8	15.09
Port Bits 1->0	53	8	15.09

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[1:0]	No	No		No		INPUT
data_i[3:2]	Yes	Yes	T5,T7,T11	Yes	T5,T6,T7	INPUT
data_i[42:4]	No	No		No		INPUT
data_i[56:43]	Unreachable	Unreachable		Unreachable		INPUT
data_i[58:57]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
data_i[60:59]	No	No		No		INPUT
data_i[62:61]	Yes	Yes	T5,T7,T11	Yes	T5,T6,T7	INPUT
data_i[63]	No	No		No		INPUT
data_o[0]	No	No		No		OUTPUT
data_o[1]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
data_o[3:2]	Yes	Yes	T5,T7,T11	Yes	T5,T6,T7	OUTPUT
data_o[56:4]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
syndrome_o[6:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.u_reg_tap.u_chk.u_chk

	Total	Covered	Percent
Totals	2	0	0.00
Total Bits	116	40	34.48
Total Bits 0->1	58	20	34.48
Total Bits 1->0	58	20	34.48

Ports	2	0	0.00
Port Bits	116	40	34.48
Port Bits 0->1	58	20	34.48
Port Bits 1->0	58	20	34.48

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
data_i[5:0]	No	No		No		INPUT
data_i[6]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
data_i[8:7]	No	No		No		INPUT
data_i[14:9]	Yes	Yes	T5,*T6,T7	Yes	T5,T6,T7	INPUT
data_i[42:15]	No	No		No		INPUT
data_i[56:43]	Unreachable	Unreachable		Unreachable		INPUT
data_i[57]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	INPUT
data_i[58]	No	No		No		INPUT
data_i[63:59]	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
data_o[5:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
data_o[6]	Yes	Yes	*T5,*T6,*T7	Yes	T5,T6,T7	OUTPUT
data_o[8:7]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
data_o[14:9]	Yes	Yes	T5,*T6,T7	Yes	T5,T6,T7	OUTPUT
data_o[15]	No	No		No		OUTPUT
data_o[56:16]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
syndrome_o[6:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR
err_o[1:0]	Excluded	Excluded		Excluded		OUTPUT	0->1:VC_COV_UNR / 1->0:VC_COV_UNR

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_reg.u_chk.u_chk

	Total	Covered	Percent
Totals	4	4	100.00
Total Bits	232	232	100.00
Total Bits 0->1	116	116	100.00
Total Bits 1->0	116	116	100.00

Ports	4	4	100.00
Port Bits	232	232	100.00
Port Bits 0->1	116	116	100.00
Port Bits 1->0	116	116	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
data_i[42:0]	Yes	Yes	*T2,*T3,*T12	Yes	T2,T3,T4	INPUT
data_i[56:43]	Unreachable	Unreachable		Unreachable		INPUT
data_i[63:57]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
data_o[56:0]	Yes	Yes	T2,T3,T12	Yes	T2,T3,T4	OUTPUT
syndrome_o[6:0]	Yes	Yes	T6,T7,T11	Yes	T6,T7,T11	OUTPUT
err_o[1:0]	Yes	Yes	T6,T7,T11	Yes	T6,T7,T11	OUTPUT

*Tests covering at least one bit in the range