Unified Coverage Report :: Module :: dmi_jtag_tap

Module : dmi_jtag_tap

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12			94.12

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dmi_jtag_tap.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_dmi_jtag.i_dmi_jtag_tap	94.12			94.12

---

Module Instance : tb.dut.u_dmi_jtag.i_dmi_jtag_tap

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.12			94.12

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.87			83.87

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
74.78			74.78				u_dmi_jtag

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
i_tck_inv	71.43			71.43

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : dmi_jtag_tap

	Total	Covered	Percent
Totals	17	16	94.12
Total Bits	34	32	94.12
Total Bits 0->1	17	16	94.12
Total Bits 1->0	17	16	94.12

Ports	17	16	94.12
Port Bits	34	32	94.12
Port Bits 0->1	17	16	94.12
Port Bits 1->0	17	16	94.12

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
tck_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
tms_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
trst_ni	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
td_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
td_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tdo_oe_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
testmode_i	No	No		No		INPUT
tck_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
dmi_clear_o	Yes	Yes	T5,T6,T7	Yes	T5,T7,T11	OUTPUT
update_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
capture_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
shift_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
tdi_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
dtmcs_select_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
dtmcs_tdo_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT
dmi_select_o	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	OUTPUT
dmi_tdo_i	Yes	Yes	T5,T6,T7	Yes	T5,T6,T7	INPUT