Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : prim_cdc_rand_delay
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_prim_cdc_rand_delay_0/rtl/prim_cdc_rand_delay.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay 100.00 100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay 100.00 100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay 100.00 100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay 100.00 100.00
tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay 100.00 100.00


Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
100.00 100.00 gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : prim_cdc_rand_delay
TotalCoveredPercent
Totals 5 5 100.00
Total Bits 10 10 100.00
Total Bits 0->1 5 5 100.00
Total Bits 1->0 5 5 100.00

Ports 5 5 100.00
Port Bits 10 10 100.00
Port Bits 0->1 5 5 100.00
Port Bits 1->0 5 5 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
prev_data_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
src_data_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
dst_data_o Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.u_combined_rstn_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay
TotalCoveredPercent
Totals 4 4 100.00
Total Bits 8 8 100.00
Total Bits 0->1 4 4 100.00
Total Bits 1->0 4 4 100.00

Ports 4 4 100.00
Port Bits 8 8 100.00
Port Bits 0->1 4 4 100.00
Port Bits 1->0 4 4 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirectionExclude Annotation
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
prev_data_i Yes Yes T5,T7,T11 Yes T5,T6,T7 INPUT
src_data_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
dst_data_o Excluded Excluded T5,T6,T7 Excluded T5,T6,T7 OUTPUT 0->1:VC_COV_UNR / 1->0:VC_COV_UNR

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay
TotalCoveredPercent
Totals 5 5 100.00
Total Bits 10 10 100.00
Total Bits 0->1 5 5 100.00
Total Bits 1->0 5 5 100.00

Ports 5 5 100.00
Port Bits 10 10 100.00
Port Bits 0->1 5 5 100.00
Port Bits 1->0 5 5 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
prev_data_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
src_data_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
dst_data_o Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_req.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay
TotalCoveredPercent
Totals 5 5 100.00
Total Bits 10 10 100.00
Total Bits 0->1 5 5 100.00
Total Bits 1->0 5 5 100.00

Ports 5 5 100.00
Port Bits 10 10 100.00
Port Bits 0->1 5 5 100.00
Port Bits 1->0 5 5 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T5,T7,T11 Yes T5,T6,T7 INPUT
prev_data_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
src_data_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
dst_data_o Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.ack_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay
TotalCoveredPercent
Totals 5 5 100.00
Total Bits 10 10 100.00
Total Bits 0->1 5 5 100.00
Total Bits 1->0 5 5 100.00

Ports 5 5 100.00
Port Bits 10 10 100.00
Port Bits 0->1 5 5 100.00
Port Bits 1->0 5 5 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T5,T7,T11 Yes T5,T6,T7 INPUT
prev_data_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
src_data_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
dst_data_o Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT

Toggle Coverage for Instance : tb.dut.u_dmi_jtag.i_dmi_cdc.i_cdc_resp.u_prim_sync_reqack.gen_rz_hs_protocol.req_sync.gen_generic.u_impl_generic.u_prim_cdc_rand_delay
TotalCoveredPercent
Totals 5 5 100.00
Total Bits 10 10 100.00
Total Bits 0->1 5 5 100.00
Total Bits 1->0 5 5 100.00

Ports 5 5 100.00
Port Bits 10 10 100.00
Port Bits 0->1 5 5 100.00
Port Bits 1->0 5 5 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
rst_ni Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
prev_data_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
src_data_i Yes Yes T5,T6,T7 Yes T5,T6,T7 INPUT
dst_data_o Yes Yes T5,T6,T7 Yes T5,T6,T7 OUTPUT

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%