Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_03/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	65976721	14845	0	0
claim_transition_if_regwen_rd_A	65976721	1023	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	65976721	14845	0	0
T10	33531	0	0	0
T36	19572	0	0	0
T62	198658	6	0	0
T67	1233	0	0	0
T94	0	9	0	0
T105	0	2	0	0
T145	0	7	0	0
T146	0	5	0	0
T147	0	3	0	0
T148	0	6	0	0
T149	0	7	0	0
T150	0	1	0	0
T151	0	18	0	0
T152	1710	0	0	0
T153	2840	0	0	0
T154	25124	0	0	0
T155	51076	0	0	0
T156	1442	0	0	0
T157	100171	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	65976721	1023	0	0
T25	39818	0	0	0
T48	44344	0	0	0
T93	240439	8	0	0
T110	0	77	0	0
T112	0	52	0	0
T158	0	17	0	0
T159	0	3	0	0
T160	0	1	0	0
T161	0	9	0	0
T162	0	255	0	0
T163	0	11	0	0
T164	0	47	0	0
T165	7861	0	0	0
T166	12075	0	0	0
T167	27953	0	0	0
T168	14684	0	0	0
T169	1454	0	0	0
T170	329068	0	0	0
T171	22925	0	0	0