Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	682628	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

867068

1

T1

14

T3

159

T4

186

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1261319	1			T1	101		T2	2		T3	261
values[0x0]	143999	1			T1	11		T2	1		T3	21
values[0x1]	144378	1			T1	5		T3	23		T4	65

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	538698	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1010998

1

T1

48

T2

1

T3

202

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7848	1			T3	6		T19	2		T20	1
valid_sources[0x01]	4227	1			T17	1		T19	11		T20	6
valid_sources[0x02]	4201	1			T17	13		T19	10		T20	7
valid_sources[0x03]	4575	1			T17	1		T19	10		T20	2
valid_sources[0x04]	5527	1			T19	13		T20	2		T47	21
valid_sources[0x05]	4408	1			T1	1		T3	18		T19	2
valid_sources[0x06]	4766	1			T1	1		T17	1		T19	2
valid_sources[0x07]	9140	1			T17	5		T19	6		T20	8
valid_sources[0x08]	5908	1			T19	1		T20	4		T33	1
valid_sources[0x09]	6195	1			T1	1		T17	7		T19	4
valid_sources[0x0a]	4831	1			T1	1		T19	7		T20	5
valid_sources[0x0b]	8330	1			T17	1		T19	14		T20	4
valid_sources[0x0c]	4916	1			T1	1		T19	5		T20	5
valid_sources[0x0d]	4434	1			T1	1		T6	2		T19	6
valid_sources[0x0e]	6033	1			T17	1		T19	19		T20	9
valid_sources[0x0f]	4302	1			T1	1		T19	4		T20	9
valid_sources[0x10]	6343	1			T17	7		T19	5		T20	1
valid_sources[0x11]	4777	1			T17	2		T19	10		T20	6
valid_sources[0x12]	4206	1			T1	1		T17	6		T19	11
valid_sources[0x13]	4018	1			T1	3		T6	1		T17	12
valid_sources[0x14]	4859	1			T17	3		T19	3		T20	2
valid_sources[0x15]	4385	1			T17	6		T19	1		T20	5
valid_sources[0x16]	4621	1			T1	1		T3	2		T17	6
valid_sources[0x17]	4626	1			T17	8		T19	13		T20	4
valid_sources[0x18]	13220	1			T17	10		T19	11		T20	1
valid_sources[0x19]	4518	1			T1	1		T17	5		T19	15
valid_sources[0x1a]	5805	1			T17	16		T19	7		T20	4
valid_sources[0x1b]	4353	1			T17	4		T19	3		T20	4
valid_sources[0x1c]	5050	1			T17	1		T19	2		T20	6
valid_sources[0x1d]	6454	1			T19	17		T20	8		T8	4
valid_sources[0x1e]	5929	1			T17	4		T19	6		T20	1
valid_sources[0x1f]	4242	1			T6	1		T17	11		T19	10
valid_sources[0x20]	6267	1			T19	3		T20	6		T34	3
valid_sources[0x21]	19999	1			T17	1		T19	6		T20	3
valid_sources[0x22]	5748	1			T17	5		T19	6		T20	1
valid_sources[0x23]	5811	1			T1	1		T16	216		T19	11
valid_sources[0x24]	4477	1			T17	4		T19	10		T20	8
valid_sources[0x25]	4288	1			T1	2		T13	1		T17	9
valid_sources[0x26]	13295	1			T19	8		T20	4		T47	31
valid_sources[0x27]	4320	1			T19	8		T20	6		T34	2
valid_sources[0x28]	4547	1			T3	29		T6	1		T17	14
valid_sources[0x29]	4609	1			T17	1		T19	4		T20	5
valid_sources[0x2a]	4483	1			T17	1		T19	3		T20	1
valid_sources[0x2b]	26835	1			T1	3		T19	7		T20	2
valid_sources[0x2c]	4841	1			T1	1		T3	7		T17	5
valid_sources[0x2d]	4880	1			T1	2		T17	2		T19	7
valid_sources[0x2e]	4446	1			T1	1		T19	1		T20	7
valid_sources[0x2f]	4142	1			T19	13		T20	4		T8	1
valid_sources[0x30]	4664	1			T1	1		T17	3		T19	14
valid_sources[0x31]	6128	1			T1	3		T17	7		T19	6
valid_sources[0x32]	5964	1			T3	25		T17	6		T19	2
valid_sources[0x33]	4539	1			T19	1		T20	4		T8	3
valid_sources[0x34]	4698	1			T17	10		T19	17		T20	4
valid_sources[0x35]	4218	1			T19	3		T20	2		T34	2
valid_sources[0x36]	4428	1			T1	1		T6	1		T19	6
valid_sources[0x37]	4540	1			T1	1		T17	7		T19	13
valid_sources[0x38]	5529	1			T17	3		T19	5		T20	5
valid_sources[0x39]	6370	1			T19	1		T20	4		T8	2
valid_sources[0x3a]	5757	1			T6	1		T17	10		T19	9
valid_sources[0x3b]	4531	1			T3	14		T17	1		T19	7
valid_sources[0x3c]	4903	1			T1	2		T17	2		T19	4
valid_sources[0x3d]	4185	1			T1	1		T17	11		T19	3
valid_sources[0x3e]	4362	1			T3	14		T17	1		T19	4
valid_sources[0x3f]	4391	1			T17	5		T19	2		T20	3
valid_sources[0x40]	4323	1			T1	1		T19	6		T20	8
valid_sources[0x41]	6205	1			T17	2		T19	3		T20	4
valid_sources[0x42]	7413	1			T19	9		T20	7		T8	2
valid_sources[0x43]	5725	1			T1	1		T3	6		T19	10
valid_sources[0x44]	4648	1			T17	6		T19	7		T20	5
valid_sources[0x45]	4364	1			T17	3		T19	2		T20	4
valid_sources[0x46]	6260	1			T1	1		T17	3		T19	9
valid_sources[0x47]	5695	1			T1	1		T17	10		T19	11
valid_sources[0x48]	9408	1			T1	1		T17	5		T19	2
valid_sources[0x49]	4359	1			T1	2		T17	10		T19	6
valid_sources[0x4a]	4583	1			T1	1		T17	1		T19	16
valid_sources[0x4b]	3984	1			T1	1		T17	3		T19	1
valid_sources[0x4c]	4425	1			T17	6		T20	2		T33	1
valid_sources[0x4d]	6236	1			T6	1		T17	19		T19	12
valid_sources[0x4e]	4161	1			T19	12		T20	2		T47	12
valid_sources[0x4f]	42685	1			T6	1		T19	7		T20	4
valid_sources[0x50]	4416	1			T1	1		T3	3		T19	1
valid_sources[0x51]	8074	1			T3	2		T19	2		T20	3
valid_sources[0x52]	4505	1			T17	2		T19	5		T20	4
valid_sources[0x53]	4452	1			T1	2		T17	8		T19	4
valid_sources[0x54]	4361	1			T19	8		T20	2		T34	3
valid_sources[0x55]	4295	1			T19	1		T20	8		T34	2
valid_sources[0x56]	5760	1			T19	3		T20	7		T47	20
valid_sources[0x57]	4379	1			T1	1		T17	2		T19	5
valid_sources[0x58]	4383	1			T17	4		T19	2		T20	2
valid_sources[0x59]	4219	1			T1	1		T17	3		T19	2
valid_sources[0x5a]	4484	1			T3	11		T19	7		T20	7
valid_sources[0x5b]	4284	1			T6	1		T17	2		T19	12
valid_sources[0x5c]	4956	1			T17	3		T19	13		T20	1
valid_sources[0x5d]	5871	1			T6	2		T17	5		T19	1
valid_sources[0x5e]	9222	1			T1	2		T17	7		T19	4
valid_sources[0x5f]	4396	1			T1	1		T17	5		T19	1
valid_sources[0x60]	4907	1			T1	1		T17	2		T19	11
valid_sources[0x61]	4363	1			T1	1		T17	1		T19	1
valid_sources[0x62]	4657	1			T6	1		T17	3		T19	16
valid_sources[0x63]	4372	1			T1	1		T6	1		T17	7
valid_sources[0x64]	6006	1			T3	4		T19	8		T20	3
valid_sources[0x65]	7341	1			T3	2		T17	4		T19	2
valid_sources[0x66]	4914	1			T1	2		T19	3		T20	2
valid_sources[0x67]	9267	1			T1	2		T3	39		T17	6
valid_sources[0x68]	5758	1			T6	3		T17	4		T19	2
valid_sources[0x69]	4249	1			T15	4		T17	15		T19	9
valid_sources[0x6a]	65680	1			T6	2		T17	3		T19	19
valid_sources[0x6b]	6854	1			T17	1		T19	8		T20	3
valid_sources[0x6c]	4166	1			T17	3		T19	5		T20	4
valid_sources[0x6d]	21962	1			T17	7		T19	14		T20	3
valid_sources[0x6e]	4414	1			T17	18		T19	4		T20	6
valid_sources[0x6f]	4441	1			T19	2		T20	1		T34	1
valid_sources[0x70]	4259	1			T17	12		T20	1		T8	1
valid_sources[0x71]	17620	1			T6	2		T17	3		T19	7
valid_sources[0x72]	4823	1			T17	6		T19	3		T47	16
valid_sources[0x73]	5108	1			T19	12		T20	9		T34	2
valid_sources[0x74]	4452	1			T1	1		T13	2		T17	1
valid_sources[0x75]	4320	1			T1	1		T17	7		T19	7
valid_sources[0x76]	4880	1			T1	1		T6	1		T17	8
valid_sources[0x77]	4848	1			T17	1		T19	8		T20	4
valid_sources[0x78]	25549	1			T3	12		T17	1		T19	12
valid_sources[0x79]	4328	1			T1	1		T17	2		T19	6
valid_sources[0x7a]	5003	1			T3	3		T19	9		T20	5
valid_sources[0x7b]	4603	1			T19	5		T20	4		T34	1
valid_sources[0x7c]	4376	1			T1	1		T17	5		T19	6
valid_sources[0x7d]	9922	1			T3	17		T6	1		T17	2
valid_sources[0x7e]	5446	1			T1	1		T17	3		T19	1
valid_sources[0x7f]	4618	1			T17	3		T19	6		T8	2
valid_sources[0x80]	4689	1			T6	2		T17	10		T19	9

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

619314

1

T1

1

T3

125

T4

80

values[0x0]

all_enables

biggest_size

124621

1

T1

9

T3

14

T4

48

values[0x1]

all_enables

biggest_size

123133

1

T1

4

T3

20

T4

58