Unified Coverage Report :: Group :: dv_base_reg_pkg::mubi_cov#(4,32'b00000000000000000000000000000101,32'b00000000000000000000000000001010)::mubi_cg

Group : dv_base_reg_pkg::mubi_cov#(4,32'b00000000000000000000000000000101,32'b00000000000000000000000000001010)::mubi_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	91.67	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

6 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
mubi4_cov_of_tb.dut.u_otp_lc_data_i_rma_token_valid_if	83.33	1	100	1	64	64
mubi4_cov_of_tb.dut.u_otp_lc_data_i_secrets_valid_if	83.33	1	100	1	64	64
mubi4_cov_of_tb.dut.u_otp_lc_data_i_test_tokens_valid_if	83.33	1	100	1	64	64
mubi4_cov_of_tb.dut.u_lc_clk_byp_ack_i_if	100.00	1	100	1	64	64
mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[0].lc_tx_if	100.00	1	100	1	64	64
mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[1].lc_tx_if	100.00	1	100	1	64	64

---

Group Instance : mubi4_cov_of_tb.dut.u_otp_lc_data_i_rma_token_valid_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_tb.dut.u_otp_lc_data_i_rma_token_valid_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance mubi4_cov_of_tb.dut.u_otp_lc_data_i_rma_token_valid_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	1	5	83.33	100	1	1	0

---

Group Instance : mubi4_cov_of_tb.dut.u_otp_lc_data_i_secrets_valid_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_tb.dut.u_otp_lc_data_i_secrets_valid_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance mubi4_cov_of_tb.dut.u_otp_lc_data_i_secrets_valid_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	1	5	83.33	100	1	1	0

---

Group Instance : mubi4_cov_of_tb.dut.u_otp_lc_data_i_test_tokens_valid_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
83.33	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_tb.dut.u_otp_lc_data_i_test_tokens_valid_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	1	5	83.33

Variables for Group Instance mubi4_cov_of_tb.dut.u_otp_lc_data_i_test_tokens_valid_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	1	5	83.33	100	1	1	0

---

Group Instance : mubi4_cov_of_tb.dut.u_lc_clk_byp_ack_i_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_clk_byp_ack_i_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_clk_byp_ack_i_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[0].lc_tx_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[0].lc_tx_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[0].lc_tx_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

---

Group Instance : mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[1].lc_tx_if

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[1].lc_tx_if

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	6	0	6	100.00

Variables for Group Instance mubi4_cov_of_tb.dut.u_lc_flash_rma_ack_i_if.gen_connect_lc_tx_items[1].lc_tx_if

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_value	6	0	6	100.00	100	1	1	0

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
false	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	343	1			T46	12		T58	16		T220	8
others[1]	339	1			T52	4		T58	10		T220	10
others[2]	359	1			T46	2		T52	4		T58	6
others[3]	507	1			T46	22		T52	2		T58	5
true	43401	1			T1	1		T2	1		T3	6

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
true	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	320	1			T46	8		T52	2		T58	6
others[1]	289	1			T46	6		T52	2		T58	10
others[2]	326	1			T46	12		T52	6		T58	6
others[3]	566	1			T46	16		T52	14		T58	8
false	43408	1			T1	1		T2	1		T3	6

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	1	5	83.33

User Defined Bins for cp_value

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
false	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	328	1			T46	3		T52	14		T58	6
others[1]	272	1			T46	8		T52	7		T58	8
others[2]	283	1			T46	4		T52	8		T58	4
others[3]	551	1			T46	12		T52	8		T58	16
true	43409	1			T1	1		T2	1		T3	6

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	157	1			T46	8		T52	1		T58	3
others[1]	165	1			T46	5		T52	5		T58	4
others[2]	159	1			T46	2		T52	4		T58	3
others[3]	270	1			T46	5		T52	3		T58	3
false	740436	1			T1	1		T2	1		T3	6
true	696181	1			T1	1		T5	1		T19	2

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	170	1			T46	3		T52	6		T58	5
others[1]	199	1			T46	6		T52	3		T58	6
others[2]	160	1			T46	7		T52	3		T58	5
others[3]	272	1			T46	4		T52	4		T58	5
false	1695239	1			T1	1		T2	1		T3	7
true	1651053	1			T3	1		T17	2		T18	3

Summary for Variable cp_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	170	1			T46	3		T52	6		T58	5
others[1]	199	1			T46	6		T52	3		T58	6
others[2]	160	1			T46	7		T52	3		T58	5
others[3]	272	1			T46	4		T52	4		T58	5
false	1695239	1			T1	1		T2	1		T3	7
true	1651053	1			T3	1		T17	2		T18	3