Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_10/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	62610153	14694	0	0
claim_transition_if_regwen_rd_A	62610153	1199	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62610153	14694	0	0
T75	237105	6	0	0
T76	0	2	0	0
T108	163425	3	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	4	0	0
T158	0	9	0	0
T159	0	14	0	0
T160	0	5	0	0
T161	0	3	0	0
T162	50269	0	0	0
T163	1698	0	0	0
T164	1288	0	0	0
T165	38150	0	0	0
T166	39704	0	0	0
T167	29483	0	0	0
T168	4099	0	0	0
T169	26125	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	62610153	1199	0	0
T86	13206	0	0	0
T155	284344	3	0	0
T156	0	3	0	0
T157	0	6	0	0
T160	0	1	0	0
T170	0	1	0	0
T171	0	3	0	0
T172	0	9	0	0
T173	0	155	0	0
T174	0	120	0	0
T175	0	2	0	0
T176	34817	0	0	0
T177	21131	0	0	0
T178	28943	0	0	0
T179	29131	0	0	0
T180	481872	0	0	0
T181	6951	0	0	0
T182	4390	0	0	0
T183	25457	0	0	0