Unified Coverage Report :: Group :: alert_esc_agent_pkg::esc_handshake_complete_cg

Group : alert_esc_agent_pkg::esc_handshake_complete_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_alert_esc_agent_0/alert_esc_agent_cov.sv

2 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
alert_esc_agent_pkg.m_esc_handshake_complete_cg	100.00	1	100	1	64	64
alert_esc_agent_pkg.m_esc_handshake_complete_cg_(1)	100.00	1	100	1	64	64

---

Group Instance : alert_esc_agent_pkg.m_esc_handshake_complete_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance alert_esc_agent_pkg.m_esc_handshake_complete_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00
Crosses	1	0	1	100.00

Variables for Group Instance alert_esc_agent_pkg.m_esc_handshake_complete_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_handshake_complete	1	0	1	100.00	100	1	1	0
cp_trans_type	1	0	1	100.00	100	1	1	0

Crosses for Group Instance alert_esc_agent_pkg.m_esc_handshake_complete_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
esc_handshake_complete	1	0	1	100.00	100	1	1	0

---

Group Instance : alert_esc_agent_pkg.m_esc_handshake_complete_cg_(1)

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance alert_esc_agent_pkg.m_esc_handshake_complete_cg_(1)

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	2	0	2	100.00
Crosses	1	0	1	100.00

Variables for Group Instance alert_esc_agent_pkg.m_esc_handshake_complete_cg_(1)

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_handshake_complete	1	0	1	100.00	100	1	1	0
cp_trans_type	1	0	1	100.00	100	1	1	0

Crosses for Group Instance alert_esc_agent_pkg.m_esc_handshake_complete_cg_(1)

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
esc_handshake_complete	1	0	1	100.00	100	1	1	0

Summary for Variable cp_handshake_complete

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_handshake_complete

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

complete

9140

1

T3

4

T4

4

T6

1

---

Summary for Variable cp_trans_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_trans_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_triggered

9140

1

T3

4

T4

4

T6

1

---

Summary for Cross esc_handshake_complete

Samples crossed: cp_handshake_complete cp_trans_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for esc_handshake_complete

Bins

cp_handshake_complete

cp_trans_type

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

complete

esc_triggered

9140

1

T3

4

T4

4

T6

1

Summary for Variable cp_handshake_complete

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_handshake_complete

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

complete

9222

1

T3

8

T4

2

T6

5

---

Summary for Variable cp_trans_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_trans_type

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_triggered

9222

1

T3

8

T4

2

T6

5

---

Summary for Cross esc_handshake_complete

Samples crossed: cp_handshake_complete cp_trans_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	1	0	1	100.00

Automatically Generated Cross Bins for esc_handshake_complete

Bins

cp_handshake_complete

cp_trans_type

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

complete

esc_triggered

9222

1

T3

8

T4

2

T6

5