Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	858327	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1047814

1

T1

13

T2

364

T3

196

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1614746	1			T1	15		T2	511		T3	248
values[0x0]	145381	1			T1	10		T2	68		T3	50
values[0x1]	146014	1			T1	6		T2	59		T3	46

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	679512	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1226629

1

T1

18

T2

423

T3

220

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	6518	1			T4	4		T13	2		T15	23
valid_sources[0x01]	6360	1			T4	11		T13	1		T15	15
valid_sources[0x02]	7117	1			T1	1		T2	4		T3	4
valid_sources[0x03]	6494	1			T3	1		T4	2		T13	2
valid_sources[0x04]	6717	1			T1	1		T2	3		T3	6
valid_sources[0x05]	8157	1			T2	1		T15	10		T16	6
valid_sources[0x06]	8506	1			T13	3		T15	21		T16	1
valid_sources[0x07]	6474	1			T2	1		T4	2		T13	1
valid_sources[0x08]	6856	1			T2	12		T3	2		T13	2
valid_sources[0x09]	6476	1			T2	1		T13	4		T15	13
valid_sources[0x0a]	6582	1			T4	2		T13	2		T15	17
valid_sources[0x0b]	8031	1			T2	6		T4	3		T13	1
valid_sources[0x0c]	6556	1			T2	5		T3	1		T13	2
valid_sources[0x0d]	6754	1			T2	7		T4	1		T14	8
valid_sources[0x0e]	6373	1			T2	9		T3	2		T13	4
valid_sources[0x0f]	6398	1			T2	2		T13	1		T15	19
valid_sources[0x10]	6602	1			T2	2		T4	1		T13	1
valid_sources[0x11]	6889	1			T3	1		T13	2		T15	11
valid_sources[0x12]	6244	1			T2	8		T4	2		T13	3
valid_sources[0x13]	6851	1			T3	2		T13	1		T15	10
valid_sources[0x14]	7725	1			T1	1		T2	3		T3	4
valid_sources[0x15]	6488	1			T2	1		T3	2		T4	1
valid_sources[0x16]	6252	1			T2	1		T3	1		T4	2
valid_sources[0x17]	9356	1			T2	3		T15	14		T7	6
valid_sources[0x18]	6802	1			T3	2		T4	1		T14	2
valid_sources[0x19]	6662	1			T3	2		T15	23		T7	1
valid_sources[0x1a]	6307	1			T2	3		T3	1		T13	3
valid_sources[0x1b]	16057	1			T2	1		T3	1		T13	5
valid_sources[0x1c]	6363	1			T2	5		T3	1		T13	2
valid_sources[0x1d]	6551	1			T2	5		T3	1		T12	1
valid_sources[0x1e]	7553	1			T2	6		T3	3		T13	1
valid_sources[0x1f]	8145	1			T2	8		T3	2		T13	1
valid_sources[0x20]	6398	1			T2	1		T3	2		T13	2
valid_sources[0x21]	6574	1			T1	1		T2	22		T4	3
valid_sources[0x22]	6572	1			T2	4		T3	1		T13	5
valid_sources[0x23]	6440	1			T2	9		T13	4		T15	9
valid_sources[0x24]	6488	1			T1	1		T3	1		T15	11
valid_sources[0x25]	6312	1			T3	3		T4	8		T13	1
valid_sources[0x26]	6321	1			T2	6		T3	1		T4	6
valid_sources[0x27]	7155	1			T3	4		T4	5		T13	1
valid_sources[0x28]	10037	1			T3	3		T13	2		T15	17
valid_sources[0x29]	6504	1			T3	1		T14	2		T15	11
valid_sources[0x2a]	6449	1			T2	2		T13	3		T15	13
valid_sources[0x2b]	6366	1			T2	14		T3	4		T13	2
valid_sources[0x2c]	6935	1			T1	1		T2	3		T3	2
valid_sources[0x2d]	6364	1			T1	1		T3	1		T13	2
valid_sources[0x2e]	6443	1			T3	1		T4	5		T13	3
valid_sources[0x2f]	6543	1			T4	1		T13	1		T14	3
valid_sources[0x30]	6528	1			T2	9		T3	3		T13	2
valid_sources[0x31]	10075	1			T2	6		T15	9		T7	7
valid_sources[0x32]	6307	1			T2	2		T4	4		T13	3
valid_sources[0x33]	13815	1			T3	2		T13	1		T15	22
valid_sources[0x34]	8545	1			T4	2		T13	1		T14	4
valid_sources[0x35]	6613	1			T3	5		T4	6		T15	16
valid_sources[0x36]	8888	1			T2	12		T4	4		T13	1
valid_sources[0x37]	9444	1			T2	4		T3	6		T4	3
valid_sources[0x38]	6492	1			T4	1		T13	3		T15	6
valid_sources[0x39]	6481	1			T3	2		T4	1		T13	1
valid_sources[0x3a]	6585	1			T3	1		T13	1		T14	2
valid_sources[0x3b]	5999	1			T1	3		T13	1		T15	14
valid_sources[0x3c]	7133	1			T3	1		T4	1		T13	3
valid_sources[0x3d]	6772	1			T3	2		T13	3		T15	22
valid_sources[0x3e]	6549	1			T1	1		T3	2		T4	1
valid_sources[0x3f]	6824	1			T3	2		T13	2		T14	1
valid_sources[0x40]	6657	1			T2	6		T3	2		T4	2
valid_sources[0x41]	36607	1			T3	1		T13	5		T15	13
valid_sources[0x42]	6277	1			T3	1		T13	2		T15	13
valid_sources[0x43]	8417	1			T2	1		T3	3		T4	11
valid_sources[0x44]	42587	1			T3	1		T4	4		T13	4
valid_sources[0x45]	6576	1			T2	3		T3	2		T13	3
valid_sources[0x46]	20642	1			T3	3		T13	5		T14	2
valid_sources[0x47]	8041	1			T1	1		T2	18		T3	1
valid_sources[0x48]	9603	1			T2	3		T3	1		T13	6
valid_sources[0x49]	6264	1			T2	8		T3	1		T15	19
valid_sources[0x4a]	6290	1			T1	1		T3	1		T13	2
valid_sources[0x4b]	6255	1			T3	1		T13	2		T15	15
valid_sources[0x4c]	6450	1			T3	1		T4	5		T13	2
valid_sources[0x4d]	7116	1			T4	6		T14	1		T15	21
valid_sources[0x4e]	6771	1			T2	12		T4	11		T13	3
valid_sources[0x4f]	6871	1			T2	6		T3	4		T4	2
valid_sources[0x50]	7761	1			T1	1		T2	9		T3	2
valid_sources[0x51]	6505	1			T13	1		T15	25		T7	3
valid_sources[0x52]	6430	1			T3	2		T4	1		T13	5
valid_sources[0x53]	6621	1			T2	2		T4	9		T13	3
valid_sources[0x54]	6746	1			T2	4		T13	2		T15	16
valid_sources[0x55]	6459	1			T2	2		T13	2		T15	20
valid_sources[0x56]	6286	1			T3	1		T13	4		T15	15
valid_sources[0x57]	6394	1			T2	2		T3	1		T13	3
valid_sources[0x58]	7653	1			T2	5		T3	5		T4	4
valid_sources[0x59]	7707	1			T2	1		T3	2		T13	1
valid_sources[0x5a]	7610	1			T1	2		T2	1		T3	3
valid_sources[0x5b]	9701	1			T3	1		T13	4		T15	10
valid_sources[0x5c]	7474	1			T2	1		T13	4		T14	2
valid_sources[0x5d]	6469	1			T2	1		T3	2		T15	20
valid_sources[0x5e]	8354	1			T3	1		T4	6		T13	2
valid_sources[0x5f]	6477	1			T3	2		T13	3		T15	2
valid_sources[0x60]	6326	1			T2	1		T3	1		T13	1
valid_sources[0x61]	6372	1			T4	1		T13	2		T15	19
valid_sources[0x62]	6324	1			T1	1		T3	3		T13	4
valid_sources[0x63]	6566	1			T15	11		T7	4		T33	61
valid_sources[0x64]	6412	1			T2	1		T3	3		T4	3
valid_sources[0x65]	6435	1			T1	1		T2	1		T3	2
valid_sources[0x66]	6455	1			T1	1		T2	5		T3	3
valid_sources[0x67]	7842	1			T3	1		T13	2		T15	8
valid_sources[0x68]	6414	1			T2	4		T13	1		T15	4
valid_sources[0x69]	8613	1			T2	1		T3	3		T13	2
valid_sources[0x6a]	7169	1			T2	4		T3	1		T13	2
valid_sources[0x6b]	8995	1			T2	2		T13	1		T15	9
valid_sources[0x6c]	8797	1			T2	6		T3	2		T4	1
valid_sources[0x6d]	8581	1			T3	1		T13	1		T15	4
valid_sources[0x6e]	6109	1			T1	1		T2	1		T4	3
valid_sources[0x6f]	9604	1			T2	5		T3	3		T4	3
valid_sources[0x70]	7996	1			T2	4		T3	1		T4	7
valid_sources[0x71]	6940	1			T13	1		T14	1		T15	11
valid_sources[0x72]	6552	1			T3	2		T13	5		T15	5
valid_sources[0x73]	6508	1			T3	5		T15	21		T16	6
valid_sources[0x74]	6602	1			T2	5		T3	2		T4	3
valid_sources[0x75]	8860	1			T3	2		T4	4		T13	3
valid_sources[0x76]	6610	1			T2	4		T13	6		T15	8
valid_sources[0x77]	7396	1			T2	18		T4	1		T13	1
valid_sources[0x78]	6504	1			T3	1		T13	1		T15	19
valid_sources[0x79]	6415	1			T2	6		T3	1		T4	1
valid_sources[0x7a]	6354	1			T4	2		T13	5		T15	6
valid_sources[0x7b]	7310	1			T2	7		T4	5		T13	2
valid_sources[0x7c]	6513	1			T4	1		T13	1		T15	18
valid_sources[0x7d]	20987	1			T3	1		T4	2		T13	3
valid_sources[0x7e]	10242	1			T3	2		T13	2		T15	16
valid_sources[0x7f]	6308	1			T2	1		T3	2		T13	3
valid_sources[0x80]	7882	1			T2	2		T14	1		T15	14

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

796997

1

T2

255

T3

115

T4

102

values[0x0]

all_enables

biggest_size

125966

1

T1

7

T2

60

T3

40

values[0x1]

all_enables

biggest_size

124851

1

T1

6

T2

49

T3

41