Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_17/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.10	100.00	83.10	99.89		100.00	87.50	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	61051224	14457	0	0
claim_transition_if_regwen_rd_A	61051224	1059	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61051224	14457	0	0
T58	0	1	0	0
T60	31823	0	0	0
T61	27872	0	0	0
T112	447584	7	0	0
T113	24635	1	0	0
T117	183484	0	0	0
T118	0	2	0	0
T130	0	4	0	0
T131	0	23	0	0
T171	0	3	0	0
T172	0	7	0	0
T173	0	13	0	0
T174	0	5	0	0
T175	18975	0	0	0
T176	1199	0	0	0
T177	4843	0	0	0
T178	45755	0	0	0
T179	45631	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	61051224	1059	0	0
T135	0	16	0	0
T136	0	10	0	0
T140	0	43	0	0
T141	0	85	0	0
T174	387143	10	0	0
T180	0	8	0	0
T181	0	16	0	0
T182	0	5	0	0
T183	0	38	0	0
T184	0	159	0	0
T185	655	0	0	0
T186	33081	0	0	0
T187	1627	0	0	0
T188	22672	0	0	0
T189	25643	0	0	0
T190	1875	0	0	0
T191	27443	0	0	0
T192	67837	0	0	0
T193	20488	0	0	0