Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	902718	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1090235

1

T1

14

T2

43

T3

300

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1700268	1			T1	5		T2	158		T3	350
values[0x0]	145989	1			T1	4		T3	76		T4	57
values[0x1]	146696	1			T1	11		T3	69		T12	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	714470	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1278483

1

T1

16

T2

65

T3

345

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	7013	1			T13	6		T14	8		T23	2
valid_sources[0x01]	8406	1			T2	1		T13	6		T14	3
valid_sources[0x02]	5698	1			T13	2		T14	4		T15	7
valid_sources[0x03]	6492	1			T4	1		T13	4		T14	4
valid_sources[0x04]	5426	1			T2	4		T13	7		T7	12
valid_sources[0x05]	5532	1			T2	1		T13	1		T14	4
valid_sources[0x06]	14930	1			T13	6		T15	2		T17	3
valid_sources[0x07]	6608	1			T13	7		T14	1		T23	1
valid_sources[0x08]	5749	1			T4	1		T13	8		T14	8
valid_sources[0x09]	5619	1			T2	4		T13	5		T14	4
valid_sources[0x0a]	9788	1			T4	1		T5	78		T13	5
valid_sources[0x0b]	5595	1			T2	1		T4	1		T13	7
valid_sources[0x0c]	5388	1			T13	12		T14	2		T15	5
valid_sources[0x0d]	6222	1			T4	5		T13	7		T14	1
valid_sources[0x0e]	5350	1			T13	6		T14	6		T15	4
valid_sources[0x0f]	5413	1			T4	1		T13	9		T14	4
valid_sources[0x10]	7073	1			T13	3		T7	2		T14	3
valid_sources[0x11]	5393	1			T4	3		T13	3		T14	3
valid_sources[0x12]	5708	1			T13	6		T7	1		T14	3
valid_sources[0x13]	6124	1			T13	3		T7	7		T14	6
valid_sources[0x14]	7198	1			T2	1		T14	6		T15	2
valid_sources[0x15]	5735	1			T13	7		T14	1		T15	9
valid_sources[0x16]	5574	1			T2	1		T13	5		T14	3
valid_sources[0x17]	5337	1			T2	1		T13	1		T14	5
valid_sources[0x18]	7385	1			T2	1		T13	3		T7	1
valid_sources[0x19]	5233	1			T4	1		T14	3		T15	3
valid_sources[0x1a]	5469	1			T4	4		T13	1		T14	1
valid_sources[0x1b]	5757	1			T2	1		T4	5		T13	4
valid_sources[0x1c]	5978	1			T13	2		T14	6		T23	1
valid_sources[0x1d]	5569	1			T2	2		T4	5		T13	1
valid_sources[0x1e]	5640	1			T4	3		T13	11		T14	1
valid_sources[0x1f]	6631	1			T13	4		T14	1		T15	3
valid_sources[0x20]	157943	1			T2	1		T13	7		T14	3
valid_sources[0x21]	5751	1			T13	2		T14	6		T15	5
valid_sources[0x22]	5976	1			T13	2		T7	3		T14	7
valid_sources[0x23]	5470	1			T13	5		T14	2		T23	1
valid_sources[0x24]	5555	1			T2	2		T15	5		T17	5
valid_sources[0x25]	7339	1			T4	2		T13	3		T14	3
valid_sources[0x26]	5668	1			T13	2		T14	2		T15	6
valid_sources[0x27]	5160	1			T13	2		T14	4		T23	1
valid_sources[0x28]	5345	1			T2	1		T4	2		T14	1
valid_sources[0x29]	5865	1			T2	3		T12	3		T13	3
valid_sources[0x2a]	5620	1			T4	1		T13	2		T14	6
valid_sources[0x2b]	6384	1			T4	4		T13	8		T15	4
valid_sources[0x2c]	16124	1			T13	1		T14	1		T15	1
valid_sources[0x2d]	5404	1			T15	9		T17	4		T32	22
valid_sources[0x2e]	5668	1			T13	2		T14	1		T15	3
valid_sources[0x2f]	5621	1			T13	5		T7	10		T14	5
valid_sources[0x30]	5623	1			T4	5		T13	5		T7	5
valid_sources[0x31]	6011	1			T2	1		T13	6		T14	3
valid_sources[0x32]	5515	1			T2	1		T13	7		T14	4
valid_sources[0x33]	8436	1			T13	5		T14	8		T15	2
valid_sources[0x34]	5441	1			T13	2		T23	1		T15	5
valid_sources[0x35]	5299	1			T13	4		T14	1		T15	5
valid_sources[0x36]	5974	1			T13	3		T14	4		T15	2
valid_sources[0x37]	8661	1			T13	5		T14	4		T15	5
valid_sources[0x38]	5755	1			T2	4		T4	2		T13	4
valid_sources[0x39]	5323	1			T2	1		T13	6		T14	7
valid_sources[0x3a]	6920	1			T13	4		T14	2		T15	2
valid_sources[0x3b]	6476	1			T4	2		T13	1		T14	6
valid_sources[0x3c]	5325	1			T4	3		T13	2		T14	1
valid_sources[0x3d]	8956	1			T4	1		T13	5		T14	2
valid_sources[0x3e]	5059	1			T13	6		T14	2		T15	3
valid_sources[0x3f]	5951	1			T13	12		T14	3		T23	3
valid_sources[0x40]	5517	1			T2	1		T4	1		T13	2
valid_sources[0x41]	7257	1			T13	2		T14	4		T15	4
valid_sources[0x42]	5678	1			T2	1		T4	2		T13	2
valid_sources[0x43]	5575	1			T13	3		T14	3		T15	5
valid_sources[0x44]	5809	1			T13	6		T14	3		T15	4
valid_sources[0x45]	5130	1			T4	2		T14	5		T15	7
valid_sources[0x46]	6668	1			T13	6		T14	4		T15	2
valid_sources[0x47]	5718	1			T2	5		T13	9		T14	6
valid_sources[0x48]	5541	1			T2	3		T13	3		T14	1
valid_sources[0x49]	5111	1			T4	3		T13	3		T14	4
valid_sources[0x4a]	5688	1			T13	1		T14	3		T23	1
valid_sources[0x4b]	5218	1			T13	4		T14	6		T17	5
valid_sources[0x4c]	5782	1			T2	1		T4	4		T13	4
valid_sources[0x4d]	6527	1			T13	5		T14	1		T15	2
valid_sources[0x4e]	5385	1			T4	1		T13	3		T14	3
valid_sources[0x4f]	6179	1			T2	1		T4	6		T13	4
valid_sources[0x50]	5530	1			T13	9		T14	2		T15	4
valid_sources[0x51]	9548	1			T2	2		T4	3		T13	1
valid_sources[0x52]	8596	1			T13	8		T14	5		T15	5
valid_sources[0x53]	6074	1			T2	1		T13	3		T14	6
valid_sources[0x54]	5622	1			T13	4		T14	2		T15	2
valid_sources[0x55]	5130	1			T13	4		T14	3		T23	1
valid_sources[0x56]	6399	1			T2	1		T13	1		T15	5
valid_sources[0x57]	5048	1			T13	1		T14	2		T15	2
valid_sources[0x58]	5544	1			T13	1		T14	2		T15	4
valid_sources[0x59]	5350	1			T13	6		T14	4		T15	4
valid_sources[0x5a]	5286	1			T4	1		T13	3		T14	5
valid_sources[0x5b]	7029	1			T2	1		T13	8		T14	2
valid_sources[0x5c]	15555	1			T2	1		T4	7		T13	5
valid_sources[0x5d]	5965	1			T4	2		T13	5		T14	7
valid_sources[0x5e]	7336	1			T13	2		T14	3		T23	1
valid_sources[0x5f]	5926	1			T13	2		T14	7		T15	4
valid_sources[0x60]	6026	1			T4	2		T13	11		T14	3
valid_sources[0x61]	5863	1			T2	2		T4	1		T13	7
valid_sources[0x62]	5709	1			T13	3		T14	4		T15	2
valid_sources[0x63]	5586	1			T2	1		T13	3		T14	7
valid_sources[0x64]	5548	1			T2	2		T13	3		T14	5
valid_sources[0x65]	5580	1			T2	1		T4	1		T13	5
valid_sources[0x66]	6238	1			T4	1		T13	7		T14	1
valid_sources[0x67]	5372	1			T13	2		T14	3		T15	8
valid_sources[0x68]	10348	1			T13	8		T14	3		T15	4
valid_sources[0x69]	5342	1			T2	4		T4	1		T13	6
valid_sources[0x6a]	8217	1			T4	2		T13	1		T14	5
valid_sources[0x6b]	5555	1			T4	1		T13	10		T14	5
valid_sources[0x6c]	5290	1			T2	2		T13	5		T14	8
valid_sources[0x6d]	20223	1			T13	7		T14	2		T15	4
valid_sources[0x6e]	6124	1			T2	1		T13	3		T14	2
valid_sources[0x6f]	5676	1			T2	1		T13	3		T14	2
valid_sources[0x70]	6485	1			T13	4		T14	5		T15	4
valid_sources[0x71]	5886	1			T2	2		T4	1		T13	7
valid_sources[0x72]	6762	1			T2	2		T4	3		T13	2
valid_sources[0x73]	5517	1			T13	6		T14	4		T15	3
valid_sources[0x74]	6576	1			T2	2		T13	8		T14	2
valid_sources[0x75]	7835	1			T2	2		T13	1		T7	6
valid_sources[0x76]	5679	1			T4	1		T13	6		T14	4
valid_sources[0x77]	5655	1			T13	3		T14	2		T15	1
valid_sources[0x78]	14552	1			T2	1		T4	1		T13	2
valid_sources[0x79]	5483	1			T13	1		T15	6		T17	4
valid_sources[0x7a]	6348	1			T2	1		T4	1		T13	5
valid_sources[0x7b]	5583	1			T4	3		T5	5		T13	2
valid_sources[0x7c]	5374	1			T2	1		T13	3		T14	7
valid_sources[0x7d]	71070	1			T4	4		T13	3		T14	3
valid_sources[0x7e]	7854	1			T4	3		T13	9		T14	7
valid_sources[0x7f]	5427	1			T13	4		T14	2		T15	2
valid_sources[0x80]	6091	1			T4	1		T13	4		T14	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

838925

1

T1

2

T2

43

T3

179

values[0x0]

all_enables

biggest_size

126315

1

T1

2

T3

64

T4

51

values[0x1]

all_enables

biggest_size

124995

1

T1

10

T3

57

T4

49