Group : dv_base_reg_pkg::mubi_cov#(8,32'h00000096,32'h00000069)::mubi_cg
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Group : dv_base_reg_pkg::mubi_cov#(8,32'h00000096,32'h00000069)::mubi_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
50.00 50.00 1 100 1 1 64 64


Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_dv_base_reg_0/dv_base_mubi_cov.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex 50.00 1 100 1 64 64




Group Instance : mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
50.00 1 100 1 64 64




Summary for Group Instance mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 5 5 50.00


Variables for Group Instance mubi8_cov_of_mubi8_cov_of_lc_ctrl_reg_block.claim_transition_if.mutex
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_value 10 5 5 50.00 100 1 1 0


Summary for Variable cp_value

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 10 5 5 50.00


User Defined Bins for cp_value

Uncovered bins
NAMECOUNTAT LEASTNUMBERSTATUS
others[1] 0 1 1
others[5] 0 1 1
others[6] 0 1 1
others[7] 0 1 1
false 0 1 1


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
others[0] 3064 1 T5 34 T7 8 T21 38
others[2] 1 1 T220 1 - - - -
others[3] 1 1 T198 1 - - - -
others[4] 2 1 T12 1 T221 1 - -
true 42391 1 T1 2 T3 18 T4 14

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