Unified Coverage Report :: Module :: lc_ctrl_fsm_cov_if

Module : lc_ctrl_fsm_cov_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_lc_ctrl_cov_0/lc_ctrl_fsm_cov_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if	96.97	100.00	90.91			100.00

---

Module Instance : tb.dut.u_lc_ctrl_fsm.u_lc_ctrl_fsm_cov_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.97	100.00	90.91			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.34	98.87	94.19		100.00	98.63	100.00	u_lc_ctrl_fsm

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : lc_ctrl_fsm_cov_if

	Line No.	Total	Covered	Percent
TOTAL		10	10	100.00
CONT_ASSIGN	71	1	1	100.00
ALWAYS	77	9	9	100.00

70                        logic token_mux_idx_error, token_mux_idx_error_prev;
71         1/1            assign token_mux_idx_error = trans_invalid_error_o & ~trans_invalid_error;
           Tests:       T1 T2 T3 
72                        event token_mux_idx_error_cov_ev;
73                        logic token_invalid_error_o_prev;
74                        event token_digest_error_cov_ev;
75                      
76                        always @(posedge clk_i or negedge rst_ni) begin
77         1/1              if (rst_ni == 0) begin
           Tests:       T1 T2 T3 
78         1/1                token_mux_idx_error_prev   <= 0;
           Tests:       T1 T2 T3 
79         1/1                token_invalid_error_o_prev <= 0;
           Tests:       T1 T2 T3 
80                          end else begin
81         1/1                token_mux_idx_error_prev   <= token_mux_idx_error;
           Tests:       T1 T2 T3 
82         1/1                token_invalid_error_o_prev <= token_invalid_error_o;
           Tests:       T1 T2 T3 
83                          end
84                      
85         1/1              if (~token_mux_idx_error_prev & token_mux_idx_error) begin
           Tests:       T1 T2 T3 
86         1/1                ->token_mux_idx_error_cov_ev;
           Tests:       T7 T15 T46 
87                          end
                        MISSING_ELSE
88                      
89         1/1              if (~token_invalid_error_o_prev & token_invalid_error_o) begin
           Tests:       T1 T2 T3 
90         1/1                ->token_digest_error_cov_ev;
           Tests:       T13 T15 T17 
91                          end
                        MISSING_ELSE

---

Cond Coverage for Module : lc_ctrl_fsm_cov_if

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       71
 EXPRESSION (trans_invalid_error_o & ((~trans_invalid_error)))
             ----------1----------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T13,T24
1	1	Covered	T7,T15,T46

 LINE       77
 EXPRESSION (rst_ni == 1'b0)
            --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       85
 EXPRESSION (((~token_mux_idx_error_prev)) & token_mux_idx_error)
             --------------1--------------   ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T7,T15,T46
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T15,T46

 LINE       89
 EXPRESSION (((~token_invalid_error_o_prev)) & token_invalid_error_o)
             ---------------1---------------   ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T13,T15,T17

---

Branch Coverage for Module : lc_ctrl_fsm_cov_if

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	77	2	2	100.00
IF	85	2	2	100.00
IF	89	2	2	100.00

77             if (rst_ni == 0) begin
               -1-  
78               token_mux_idx_error_prev   <= 0;
                 ==>
79               token_invalid_error_o_prev <= 0;
80             end else begin
81               token_mux_idx_error_prev   <= token_mux_idx_error;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

85             if (~token_mux_idx_error_prev & token_mux_idx_error) begin
               -1-  
86               ->token_mux_idx_error_cov_ev;
                 ==>
87             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T7,T15,T46
0	Covered	T1,T2,T3

89             if (~token_invalid_error_o_prev & token_invalid_error_o) begin
               -1-  
90               ->token_digest_error_cov_ev;
                 ==>
91             end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T13,T15,T17
0	Covered	T1,T2,T3