Unified Coverage Report :: Module :: lc_ctrl_csr_assert_fpv

Module : lc_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_09_23/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_fpv_lc_ctrl_csr_assert_0/lc_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.lc_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.lc_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.47	100.00	83.10	99.89		100.00	84.38	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : lc_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	68930294	14343	0	0
claim_transition_if_regwen_rd_A	68930294	1664	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68930294	14343	0	0
T52	38715	0	0	0
T76	1829	0	0	0
T102	103472	1	0	0
T103	0	7	0	0
T104	0	2	0	0
T114	0	10	0	0
T115	0	8	0	0
T149	0	5	0	0
T150	0	3	0	0
T151	0	5	0	0
T152	0	16	0	0
T153	0	4	0	0
T154	2123	0	0	0
T155	1350	0	0	0
T156	40969	0	0	0
T157	99076	0	0	0
T158	35475	0	0	0
T159	9250	0	0	0
T160	106861	0	0	0

claim_transition_if_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	68930294	1664	0	0
T85	3497	0	0	0
T117	0	43	0	0
T119	0	81	0	0
T121	0	34	0	0
T124	0	238	0	0
T161	292010	8	0	0
T162	0	9	0	0
T163	0	9	0	0
T164	0	222	0	0
T165	0	210	0	0
T166	0	24	0	0
T167	42706	0	0	0
T168	28671	0	0	0
T169	33462	0	0	0
T170	20754	0	0	0
T171	29454	0	0	0
T172	1221	0	0	0
T173	33370	0	0	0
T174	1240	0	0	0