Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_02/lc_ctrl_volatile_unlock_enabled-sim-vcs/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_lc_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	865781	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

1055172

1

T1

14

T2

258

T3

194

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1628478	1			T1	5		T2	389		T3	164
values[0x0]	145614	1			T1	6		T2	33		T3	63
values[0x1]	146861	1			T1	9		T2	37		T3	65

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	686129	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1234824

1

T1

14

T2

306

T3

218

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	5547	1			T13	1		T4	6		T17	20
valid_sources[0x01]	6007	1			T1	1		T2	2		T4	15
valid_sources[0x02]	10110	1			T2	2		T13	2		T4	1
valid_sources[0x03]	5489	1			T2	4		T4	2		T17	16
valid_sources[0x04]	5467	1			T4	4		T17	12		T6	3
valid_sources[0x05]	5659	1			T2	1		T13	1		T4	1
valid_sources[0x06]	7039	1			T2	3		T13	2		T4	8
valid_sources[0x07]	5382	1			T2	3		T13	1		T4	9
valid_sources[0x08]	5979	1			T1	1		T4	4		T17	17
valid_sources[0x09]	5797	1			T2	1		T13	1		T4	1
valid_sources[0x0a]	8104	1			T2	3		T4	1		T17	11
valid_sources[0x0b]	7209	1			T1	1		T2	1		T13	2
valid_sources[0x0c]	5480	1			T2	1		T13	2		T4	7
valid_sources[0x0d]	5285	1			T2	1		T4	8		T17	15
valid_sources[0x0e]	6820	1			T2	4		T17	18		T19	18
valid_sources[0x0f]	12070	1			T2	1		T13	1		T4	9
valid_sources[0x10]	7115	1			T2	3		T13	1		T16	1
valid_sources[0x11]	5367	1			T2	1		T13	1		T4	2
valid_sources[0x12]	5699	1			T2	1		T4	3		T17	19
valid_sources[0x13]	5514	1			T2	2		T13	2		T4	11
valid_sources[0x14]	6052	1			T2	2		T13	1		T4	3
valid_sources[0x15]	5953	1			T4	3		T17	12		T6	3
valid_sources[0x16]	5850	1			T2	1		T4	7		T17	10
valid_sources[0x17]	7489	1			T4	5		T17	3		T6	4
valid_sources[0x18]	5741	1			T4	2		T17	13		T18	6
valid_sources[0x19]	14137	1			T2	1		T13	3		T4	10
valid_sources[0x1a]	6020	1			T2	2		T4	6		T14	8
valid_sources[0x1b]	7015	1			T4	1		T17	12		T19	21
valid_sources[0x1c]	5577	1			T4	2		T17	13		T6	1
valid_sources[0x1d]	5981	1			T2	3		T13	2		T17	18
valid_sources[0x1e]	5626	1			T1	1		T2	3		T4	1
valid_sources[0x1f]	8627	1			T4	4		T17	16		T19	26
valid_sources[0x20]	7426	1			T2	1		T4	6		T17	10
valid_sources[0x21]	5734	1			T17	15		T19	18		T34	1
valid_sources[0x22]	5471	1			T2	5		T13	2		T4	4
valid_sources[0x23]	5953	1			T2	1		T4	4		T17	15
valid_sources[0x24]	7104	1			T2	2		T17	7		T6	1
valid_sources[0x25]	5373	1			T2	4		T13	1		T4	6
valid_sources[0x26]	5703	1			T1	1		T2	3		T4	7
valid_sources[0x27]	5668	1			T2	1		T13	1		T4	6
valid_sources[0x28]	102855	1			T1	1		T2	3		T17	12
valid_sources[0x29]	6890	1			T1	1		T4	1		T17	17
valid_sources[0x2a]	5539	1			T4	9		T17	22		T19	31
valid_sources[0x2b]	5759	1			T2	2		T4	5		T17	15
valid_sources[0x2c]	5352	1			T2	5		T4	11		T17	15
valid_sources[0x2d]	5277	1			T4	4		T17	14		T18	4
valid_sources[0x2e]	6730	1			T2	2		T4	11		T17	17
valid_sources[0x2f]	5661	1			T2	1		T13	2		T4	6
valid_sources[0x30]	9455	1			T4	6		T17	18		T19	19
valid_sources[0x31]	5691	1			T2	1		T4	17		T14	31
valid_sources[0x32]	5850	1			T2	1		T13	2		T4	6
valid_sources[0x33]	5503	1			T2	3		T4	1		T17	15
valid_sources[0x34]	14559	1			T2	1		T13	2		T4	2
valid_sources[0x35]	5249	1			T2	3		T4	9		T17	11
valid_sources[0x36]	9362	1			T2	1		T4	2		T17	19
valid_sources[0x37]	5431	1			T2	2		T4	9		T17	12
valid_sources[0x38]	6805	1			T2	1		T4	1		T17	16
valid_sources[0x39]	5714	1			T2	1		T4	25		T17	14
valid_sources[0x3a]	74099	1			T2	2		T4	4		T17	15
valid_sources[0x3b]	6523	1			T2	5		T13	1		T4	8
valid_sources[0x3c]	5458	1			T4	9		T17	9		T6	1
valid_sources[0x3d]	5393	1			T2	3		T4	6		T17	19
valid_sources[0x3e]	6092	1			T2	1		T4	7		T17	10
valid_sources[0x3f]	6007	1			T13	1		T4	2		T17	13
valid_sources[0x40]	9594	1			T2	1		T4	2		T17	17
valid_sources[0x41]	5872	1			T2	4		T4	8		T17	16
valid_sources[0x42]	6234	1			T2	4		T4	6		T17	18
valid_sources[0x43]	5628	1			T2	4		T13	1		T4	2
valid_sources[0x44]	5957	1			T2	1		T4	3		T17	14
valid_sources[0x45]	7174	1			T4	1		T17	12		T18	15
valid_sources[0x46]	5567	1			T1	1		T2	2		T4	4
valid_sources[0x47]	7161	1			T2	3		T4	10		T17	25
valid_sources[0x48]	7815	1			T2	1		T17	14		T18	3
valid_sources[0x49]	5541	1			T2	1		T4	7		T14	44
valid_sources[0x4a]	5692	1			T4	7		T17	10		T19	26
valid_sources[0x4b]	5523	1			T2	2		T13	2		T4	6
valid_sources[0x4c]	5605	1			T2	2		T4	17		T17	9
valid_sources[0x4d]	5468	1			T1	1		T2	2		T13	1
valid_sources[0x4e]	7743	1			T2	1		T13	1		T4	14
valid_sources[0x4f]	6948	1			T2	1		T4	1		T17	15
valid_sources[0x50]	5652	1			T13	1		T4	12		T17	22
valid_sources[0x51]	5819	1			T13	1		T4	10		T17	25
valid_sources[0x52]	5810	1			T2	1		T4	4		T16	1
valid_sources[0x53]	5484	1			T2	2		T4	14		T17	19
valid_sources[0x54]	5467	1			T2	5		T4	14		T14	28
valid_sources[0x55]	6270	1			T2	1		T13	3		T4	2
valid_sources[0x56]	7128	1			T2	3		T4	1		T17	11
valid_sources[0x57]	5644	1			T2	2		T4	2		T17	12
valid_sources[0x58]	5824	1			T2	5		T17	14		T19	25
valid_sources[0x59]	5946	1			T2	2		T4	4		T17	19
valid_sources[0x5a]	5995	1			T2	2		T4	3		T14	26
valid_sources[0x5b]	7320	1			T2	3		T4	2		T16	1
valid_sources[0x5c]	5670	1			T2	3		T4	7		T17	19
valid_sources[0x5d]	9769	1			T2	1		T4	2		T17	17
valid_sources[0x5e]	6876	1			T17	14		T19	26		T8	1
valid_sources[0x5f]	6702	1			T1	1		T2	2		T4	2
valid_sources[0x60]	5684	1			T13	2		T4	1		T14	4
valid_sources[0x61]	5551	1			T2	2		T17	22		T19	19
valid_sources[0x62]	5596	1			T2	4		T4	9		T17	14
valid_sources[0x63]	5507	1			T2	1		T4	1		T17	18
valid_sources[0x64]	7155	1			T2	1		T4	2		T17	14
valid_sources[0x65]	6609	1			T2	3		T13	2		T4	7
valid_sources[0x66]	5994	1			T4	3		T17	10		T6	1
valid_sources[0x67]	6082	1			T2	4		T4	6		T17	11
valid_sources[0x68]	5519	1			T2	1		T4	10		T17	12
valid_sources[0x69]	6081	1			T2	1		T4	11		T17	13
valid_sources[0x6a]	5529	1			T1	1		T2	1		T4	4
valid_sources[0x6b]	5662	1			T2	1		T13	2		T4	7
valid_sources[0x6c]	9321	1			T2	1		T17	11		T19	20
valid_sources[0x6d]	5616	1			T4	3		T17	20		T18	4
valid_sources[0x6e]	5519	1			T2	2		T13	1		T4	19
valid_sources[0x6f]	7447	1			T4	9		T17	10		T19	22
valid_sources[0x70]	7442	1			T13	1		T4	9		T17	11
valid_sources[0x71]	5673	1			T2	3		T4	4		T17	18
valid_sources[0x72]	6800	1			T2	4		T17	11		T18	19
valid_sources[0x73]	5825	1			T2	2		T4	2		T17	17
valid_sources[0x74]	5682	1			T4	3		T17	11		T19	18
valid_sources[0x75]	7143	1			T2	4		T4	15		T17	13
valid_sources[0x76]	7320	1			T4	4		T17	26		T18	2
valid_sources[0x77]	5776	1			T2	1		T4	4		T17	15
valid_sources[0x78]	5639	1			T2	5		T17	14		T19	24
valid_sources[0x79]	5695	1			T2	1		T4	3		T17	12
valid_sources[0x7a]	9761	1			T2	3		T4	2		T17	13
valid_sources[0x7b]	5655	1			T4	9		T17	17		T6	1
valid_sources[0x7c]	5772	1			T2	3		T4	5		T17	11
valid_sources[0x7d]	7054	1			T2	3		T4	4		T17	8
valid_sources[0x7e]	5814	1			T2	3		T4	3		T17	15
valid_sources[0x7f]	6979	1			T2	1		T4	4		T17	10
valid_sources[0x80]	5407	1			T2	2		T4	8		T17	7

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

803624

1

T1

2

T2

201

T3

84

values[0x0]

all_enables

biggest_size

126011

1

T1

5

T2

28

T3

54

values[0x1]

all_enables

biggest_size

125537

1

T1

7

T2

29

T3

56